Patents by Inventor Jong Won Lim

Jong Won Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220199305
    Abstract: An inductor includes a first magnetic body having a toroidal shape and having a ferrite; and a second magnetic body configured to be different from the first magnetic body and including a metal ribbon, wherein the second magnetic body includes an outer magnetic body disposed on an outer circumferential surface of the first magnetic body and an inner magnetic body disposed on an inner circumferential surface of the first magnetic body, and each of the outer magnetic body and inner magnetic body is wound in a plurality of layers in a circumferential direction of the first magnetic body.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 23, 2022
    Inventors: Mi Jin Lee, Ji Yeon Song, Yu Seon Kim, Jong Wook Lim, Seok Bae, Sang Won Lee
  • Publication number: 20220190428
    Abstract: Disclosed is a method for manufacturing a battery pack which has an upper plate configured to have a seating surface, on which battery modules are seated, and a plurality of members configured to separate the seating surface of the upper plate into a plurality of regions. The method includes calculating height tolerances of the seating surface in the respective regions, determining application amounts of the gap filler in the respective regions based on the calculated height tolerances in the respective regions, and applying the determined application amounts of the gap filler in the respective regions.
    Type: Application
    Filed: August 11, 2021
    Publication date: June 16, 2022
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Hae Kyu LIM, Jeong Hun SEO, Yun Ho KIM, Ji Woong JUNG, Tae Hyuck KIM, Gyung Hoon SHIN, Jong Wook LEE, In Gook SON, Wu Hyun KIM, Jae Hyeon JU, Kang Won LEE, Yong Hwan CHOI, Yu Ri OH, Hwi MOON, Young O LEE, Jae Won LEE, Jae Ho BAE
  • Patent number: 11350672
    Abstract: Provided is a device including: a battery configured to supply power; a heater configured to heat an aerosol generating material by receiving power from the battery; a sensor; at least one output unit; and a controller, wherein the controller detects a user's puff by using the sensor and controls at least one output unit based on puff characteristic data based on a result of the detection.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: June 7, 2022
    Assignee: KT&G CORPORATION
    Inventors: Hun Il Lim, Jong Sub Lee, Dae Nam Han, Jang Uk Lee, Jung Ho Han, Jin Young Yoon, Young Lea Kim, Ji Soo Jang, Wang Seop Lim, Moon Bong Lee, Soung Ho Ju, Du Jin Park, Seong Won Yoon
  • Patent number: 11355452
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 7, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dong Won Son, Byeonghoon Kim, Sung Ho Choi, Sung Jae Lim, Jong Ho Shin, SungWon Cho, ChangOh Kim, KyoungHee Park
  • Patent number: 11350663
    Abstract: Provided is an aerosol generating system including a holder configured to generate aerosol by heating a cigarette; and a cradle including an inner space into which the holder is inserted. The holder is configured to be tiltable with respect the cradle. The holder is inserted into the inner space of the cradle and then tilted to generate the aerosol.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 7, 2022
    Assignee: KT&G CORPORATION
    Inventors: Jung Ho Han, Jang Uk Lee, Hun Il Lim, Jong Sub Lee, Dae Nam Han, Jin Young Yoon, Young Lea Kim, Ji Soo Jang, Wang Seop Lim, Moon Bong Lee, Soung Ho Ju, Du Jin Park, Seong Won Yoon
  • Publication number: 20220162310
    Abstract: The present invention relates to: an antibody to T cell Immunoreceptor with Ig and Tyrosine-Based Inhibitory Motif Domains (TIGIT), or an antigen-binding fragment thereof; a nucleic acid encoding same; a vector carrying the nucleic acid; a cell transformed with the vector; a method for producing the antibody or the antigen-binding fragment thereof; and a composition and a composition for combined administration, which comprise same and are for preventing or treating cancer.
    Type: Application
    Filed: May 22, 2020
    Publication date: May 26, 2022
    Inventors: Hye-Young PARK, Eun Jung SONG, Eun Hee LEE, Hye In YUM, Hye Mi NAM, Mun Kyung KIM, Jee Won LEE, Joong Hyuk SHEEN, Min Kyu HUR, So Jung LIM, Ok Jae LIM, Yang Mi LIM, Jong Hwa WON
  • Publication number: 20220045679
    Abstract: Provided is a single pole double through (SPDT) switch including a series switching unit including first and second series switching elements commonly connected to a common input port, and a shunt switching unit including a plurality of shunt switching elements connected in parallel to a first signal path connecting the common input port to a first output port and a second signal path connecting the common input port to a second output port, wherein first and second inductors are respectively connected to gate terminals of the first and second series switching elements.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 10, 2022
    Inventors: Youn Sub NOH, Soo Cheol KANG, Seong Il KIM, Hae Cheon KIM, Ho Kyun AHN, Sang Heung LEE, Jong Won LIM, Sung Jae CHANG, Hyun Wook JUNG
  • Publication number: 20220045022
    Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 10, 2022
    Inventors: Sang Heung LEE, Soo Cheol KANG, Seong Il KIM, Hae Cheon KIM, Youn Sub NOH, Ho Kyun AHN, Jong Won LIM, Sung Jae CHANG, Hyun Wook JUNG
  • Publication number: 20220020671
    Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dong Yun JUNG, Hyun Gyu JANG, Sung Kyu KWON, Kun Sik PARK, Jong Il WON, Seong Hyun LEE, Jong Won LIM, Doo Hyung CHO
  • Publication number: 20210335681
    Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 28, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyun Gyu JANG, Dong Yun JUNG, Doo Hyung CHO, Kun Sik PARK, Jong Won LIM
  • Patent number: 10608102
    Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 31, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Min Jeong Shin, Jeong Jin Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Hyung Seok Lee, Jong-Won Lim, Sungjae Chang, Hyunwook Jung, Kyu Jun Cho, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Sang-Heung Lee, Jongmin Lee, Hong Gu Ji
  • Patent number: 10256811
    Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 9, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Woojin Chang, Jong-Won Lim, Dong Min Kang, Dong-Young Kim, Seong-il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Min Jeong Shin, Hokyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jongmin Lee, Sungjae Chang, Yoo Jin Jang, Hyunwook Jung, Kyu Jun Cho, Hong Gu Ji
  • Publication number: 20190103483
    Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
    Type: Application
    Filed: September 20, 2018
    Publication date: April 4, 2019
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hokyun AHN, Min Jeong SHIN, Jeong Jin KIM, Hae Cheon KIM, Jae Won DO, Byoung-Gue MIN, Hyung Sup YOON, Hyung Seok LEE, Jong-Won LIM, Sungjae CHANG, Hyunwook JUNG, Kyu Jun CHO, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Sang-Heung LEE, Jongmin LEE, Hong Gu JI
  • Publication number: 20190081166
    Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.
    Type: Application
    Filed: July 6, 2018
    Publication date: March 14, 2019
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae Won DO, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Hae Cheon KIM, Byoung-Gue MIN, Min Jeong SHIN, Hokyun AHN, Hyung Sup YOON, Sang-Heung LEE, Jongmin LEE, Jong-Won LIM, Sungjae CHANG, Yoo Jin JANG, Hyunwook JUNG, Kyu Jun CHO, Hong Gu JI
  • Patent number: 10134854
    Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Dong Min Kang, Yong-Hwan Kwon, Dong-Young Kim, Seong Il Kim, Hae Cheon Kim, Eun Soo Nam, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho
  • Publication number: 20180145684
    Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
    Type: Application
    Filed: July 20, 2017
    Publication date: May 24, 2018
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Woojin CHANG, Jong-Won LIM, Dong Min KANG, Dong-Young KIM, Seong-il KIM, Hae Cheon KIM, Jae Won DO, BYOUNG-GUE MIN, Min Jeong SHIN, Hokyun AHN, Hyung Sup YOON, Sang-Heung LEE, JONGMIN LEE, Sungjae CHANG, Yoo Jin JANG, HYUNWOOK JUNG, Kyu Jun CHO, Hong Gu JI
  • Patent number: 9899226
    Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Hae Cheon Kim, Jong Won Lim, Dong Min Kang, Yong Hwan Kwon, Seong Il Kim, Zin Sig Kim, Eun Soo Nam, Byoung Gue Min, Hyung Sup Yoon, Kyung Ho Lee, Jong Min Lee, Kyu Jun Cho
  • Patent number: 9837719
    Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the m
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 5, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong-Young Kim, Dong Min Kang, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Ho Kyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Yoo Jin Jang, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
  • Patent number: 9780176
    Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 3, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong Min Lee, Byoung-Gue Min, Hyung Sup Yoon, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Ho Kyun Ahn, Sang-Heung Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
  • Publication number: 20170236909
    Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
    Type: Application
    Filed: August 26, 2016
    Publication date: August 17, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun AHN, Dong Min KANG, Yong-Hwan KWON, Dong-Young KIM, SEONG IL KIM, Hae Cheon KIM, Eun Soo NAM, Jae Won DO, Byoung-Gue MIN, Hyung Sup YOON, Sang-Heung LEE, Jong Min LEE, Jong-Won LIM, Hyun Wook JUNG, Kyu Jun CHO