Patents by Inventor Jong Won Lim
Jong Won Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9224830Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.Type: GrantFiled: June 11, 2013Date of Patent: December 29, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Il Kim, Jong-Won Lim, Dong Min Kang, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Byoung-Gue Min, Jongmin Lee, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9209266Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.Type: GrantFiled: November 26, 2014Date of Patent: December 8, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Won Lim, Ho Kyun Ahn, Young Rak Park, Dong Min Kang, Woo Jin Chang, Seong-il Kim, Sung Bum Bae, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20150349736Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.Type: ApplicationFiled: March 23, 2015Publication date: December 3, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Heung LEE, Dong Min KANG, SEONG IL KIM, Ho Kyun AHN, Hyung Sup YOON, Jong Won LIM, Chull Won JU
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Patent number: 9178474Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.Type: GrantFiled: July 25, 2013Date of Patent: November 3, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang-Heung Lee, Seong-il Kim, Dong Min Kang, Jong-Won Lim, Chull Won Ju, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9166011Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.Type: GrantFiled: July 10, 2014Date of Patent: October 20, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong Il Kim, Dong Min Kang, Sang Heung Lee, Ho Kyun Ahn, Hyung Sup Yoon, Byoung Gue Min, Jong Won Lim
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Patent number: 9165896Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.Type: GrantFiled: August 7, 2014Date of Patent: October 20, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hae Cheon Kim, Ho Kyun Ahn, Byoung Gue Min, Hyung Sup Yoon, Jong Won Lim
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Patent number: 9159612Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: GrantFiled: September 9, 2013Date of Patent: October 13, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20150270822Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.Type: ApplicationFiled: September 5, 2014Publication date: September 24, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Min KANG, Seong Il KIM, Sang Heung LEE, Chull Won JU, Ho Kyun AHN, Hyung Sup YOON, Jong Won LIM
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Publication number: 20150236108Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.Type: ApplicationFiled: July 10, 2014Publication date: August 20, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Seong Il KIM, Dong Min KANG, Sang Heung LEE, Ho Kyun AHN, Hyung Sup YOON, Byoung Gue MIN, Jong Won LIM
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Publication number: 20150207233Abstract: Disclosed is a dielectric resonator antenna. The dielectric resonator antenna includes: a dielectric resonator; an antenna layer formed inside the dielectric resonator, and including a plurality of vias positioned at a surrounding area of the dielectric resonator; a metal pattern forming an opened surface in an upper portion of the antenna layer; a dielectric layer configured to cover the metal pattern on the dielectric resonator; an internal ground pattern including a coupling aperture for inputting a signal into the dielectric resonator under the dielectric resonator; and a feeding layer including a strip transmission line for transmitting a signal to the dielectric resonator, and positioned under the antenna layer.Type: ApplicationFiled: July 22, 2014Publication date: July 23, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Young KIM, Jong Won LIM, Cheon Soo KIM
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Publication number: 20150206847Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.Type: ApplicationFiled: August 7, 2014Publication date: July 23, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Hae Cheon KIM, Ho Kyun AHN, Byoung Gue MIN, Hyung Sup YOON, Jong Won LIM
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Publication number: 20150194494Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.Type: ApplicationFiled: April 2, 2014Publication date: July 9, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Ho Kyun AHN, Hae Cheon KIM, Zin Sig KIM, Sang Heung LEE, Byoung Gue MIN, Hyung Sup YOON, Dong Min KANG, Seong Il KIM, Jong Min LEE, Jong Won LIM, Yong Hwan KWON, Eun Soo NAM
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Publication number: 20150171188Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue MIN, Jong-Won LIM, Hokyun AHN, Seong-Il Kim, Sang Heung LEE, Dong Min KANG, Chull Won JU, Jae Kyoung MUN
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Publication number: 20150144961Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.Type: ApplicationFiled: February 7, 2014Publication date: May 28, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Hyung Sup YOON, Byoung Gue MIN, Ho Kyun AHN, Jong Won LIM, Dong Min KANG, Jong Min LEE
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Publication number: 20150129890Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: ApplicationFiled: December 29, 2014Publication date: May 14, 2015Inventors: Hokyun AHN, Jong-Won LIM, Jeong-Jin KIM, Hae Cheon KIM, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 9012920Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded.Type: GrantFiled: April 22, 2013Date of Patent: April 21, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Chull Won Ju, Hae Cheon Kim, Hyung Sup Yoon, Woo Jin Chang, Sang-Heung Lee, Dong-Young Kim, Jong-Won Lim, Dong Min Kang, Ho Kyun Ahn, Jong Min Lee, Eun Soo Nam
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Publication number: 20150087142Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.Type: ApplicationFiled: November 26, 2014Publication date: March 26, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Won LIM, Ho Kyun AHN, Young Rak PARK, Dong Min KANG, Woo Jin CHANG, Seong-il KIM, Sung Bum BAE, Sang-Heung LEE, Hyung Sup YOON, Chull Won JU, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8952422Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: GrantFiled: June 7, 2013Date of Patent: February 10, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8941231Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: GrantFiled: July 10, 2013Date of Patent: January 27, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Young Rak Park, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8937002Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: GrantFiled: March 31, 2014Date of Patent: January 20, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Bum Bae, Eun Soo Nam, Jae Kyoung Mun, Sung Bock Kim, Hae Cheon Kim, Chull Won Ju, Sang Choon Ko, Jong-Won Lim, Ho Kyun Ahn, Woo Jin Chang, Young Rak Park