Abstract: The present disclosure provides a polishing pad, which may maintain polishing performances required for a polishing process, such as a removal rate and a polishing profile, minimize defects that may occur on a wafer during the polishing process, and polish layers of different materials so as to have the same level of flatness even when the layers are polished at the same time, and a method for producing the polishing pad. In addition, according to the present disclosure, it is possible to determine a polishing pad, which shows an optimal removal rate selectivity along with excellent performance in a CMP process, through the physical property values of the polishing pad without a direct polishing test.

Abstract: Provided is a polishing pad including a polishing layer, wherein the nuclear magnetic resonance (NMR) 13C spectrum of a processed composition prepared by adding 1 g of the polishing layer to a 0.3 M aqueous solution of potassium hydroxide (KOH) and allowing the mixture to react in a closed container at a temperature of 150° C. for 48 hours includes a first peak appearing at 15 ppm to 18 ppm, a second peak appearing at 9 ppm to 11 ppm, and a third peak appearing at 138 ppm to 143 ppm, and the area ratio of the third peak to the second peak is about 5:1 to about 10:1. The polishing pad may exhibit physical properties corresponding to the above-described peak characteristics, thereby achieving a removal rate and defect prevention performance within desired ranges in polishing of a polishing target.

Abstract: The present disclosure relates to a polishing pad, a method of manufacturing the polishing pad, and a method of manufacturing a semiconductor device using the same. In the polishing pad, an unexpanded solid-phase blowing agent is included in a polishing composition when a polishing layer is manufactured, and the unexpanded solid-phase blowing agent is expanded during a curing process to form a plurality of uniform pores in the polishing layer, such that defects occurring on a surface of the semiconductor substrate may be prevented. In addition, the present disclosure may provide a method of manufacturing a semiconductor device to which the polishing pad is applied.

Abstract: In the composition according to the embodiment, the composition of oligomers that constitute the chains in a urethane-based prepolymer may be adjusted to control the physical properties thereof such as gelation time. Thus, since the micropore characteristics, polishing rate, and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled, it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: The present disclosure relates to an endpoint detection window of a polishing pad for use in a polishing process. The polishing pad may prevent an error in detection of the endpoint of the polishing process by preventing a difference in endpoint detection performance from occurring due to a difference in the wavelength of a laser between polishing apparatuses. The present disclosure may also provide a method of fabricating a semiconductor device using the polishing pad.

Abstract: Provided is a polishing pad including a polishing layer, wherein the nuclear magnetic resonance (NMR) 13C spectrum of a processed composition prepared by adding 1 g of the polishing layer to a 0.3 M aqueous solution of potassium hydroxide (KOH) and allowing the mixture to react in a closed container at a temperature of 150° C. for 48 hours includes a first peak appearing at 15 ppm to 18 ppm, a second peak appearing at 9 ppm to 11 ppm, a third peak appearing at 138 ppm to 143 ppm, and a fourth peak appearing at 55 ppm to 65 ppm, and the softening control index calculated by Equation 1 is 0.10 to 0.45. The polishing pad includes the polishing layer having physical properties corresponding to the softening control index, and thus may exhibit a removal rate and defect prevention performance within desired ranges in polishing of a polishing target.

Abstract: Embodiments relate to a leakage-proof polishing pad for use in a chemical mechanical planarization (CMP) process and a process for producing the same.

Abstract: The present invention provides a polishing pad, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad, the surface zeta potential and its ratio of the polishing surface are controlled to specific ranges according to the type of polishing slurry, whereby it is possible to improve the characteristics of scratches and surface defects appearing on the surface of the semiconductor substrate and to further enhance the polishing rate.

Abstract: In the composition according to an embodiment, the weight ratio of toluene 2,4-diisocyanate in which one NCO group is reacted and unreacted toluene 2,6-diisocyanate in the urethane-based prepolymer is adjusted, whereby such physical properties as gelation time can be controlled. Thus, the polishing rate and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled while it has a hardness suitable for a soft pad, whereby it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductor devices. The polishing pad may secure excellent polishing rate and within-wafer non-uniformity by controlling the physical properties such as initial load resistivity and compressive elasticity of the cushion layer and/or the laminate as defined by Equations 1 and 2: L ? R L ? ( % ) = T ? 1 ? L - T ? 2 ? L T ? 1 ? L - T ? 3 ? L × 100 [ Equation ? ? 1 ] C ? E L ? ( % ) = T ? 4 ? L - T ? 3 ? L T ? 2 ? L - T ? 3 ? L × 1 ? 00.

Abstract: An embodiment relates to a polishing pad which is used in a chemical mechanical planarization (CMP) process and has excellent airtightness, wherein the polishing pad is excellent in airtightness of a window opening and thus can prevent water leakage that may occur during a CMP process.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiments, the number average diameter (Da) and number median diameter (Dm) of a plurality of pores are adjusted to achieve a specific range of the Ed value (Equation 1). As a result, an excellent polishing rate and within-wafer non-uniformity can be achieved.

Abstract: The embodiments provide a polishing pad, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to an embodiment, the average value of the modulus of the pore region and that of the non-pore region is adjusted to 0.5 GPa to 1.6 GPa, whereby it is possible to achieve an excellent life span, to improve the scratches and surface defects appearing on the surface of a semiconductor substrate, and to further enhance the polishing rate.

Abstract: The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.

Abstract: The polishing pad according to an embodiment comprises a multifunctional low-molecular-weight compound as one of the polymerization units of the polyurethane-based resin that constitutes the polishing layer, thereby reducing the unreacted diisocyanate monomer in the production process to enhance the processability and quality and to increase the crosslinking density. Thus, the polishing pad may be applied to a process of preparing a semiconductor device, which comprises a CMP process, to provide a semiconductor device such as a wafer of excellent quality.

Abstract: The polishing pad according to an embodiment adjusts the content of elements present in the polishing layer, thereby controlling the bonding strength between the polishing pad and the polishing particles and enhancing the bonding strength between the polishing particles and the semiconductor substrate (or wafer), resulting in an increase in the polishing rate. It is possible to enhance not only the mechanical properties of the polishing pad such as hardness, tensile strength, elongation, and modulus, but also the polishing rate for both a tungsten layer or an oxide layer. Accordingly, it is possible to efficiently fabricate a semiconductor device of excellent quality using the polishing pad.

Abstract: The composition according to an embodiment employs a mixture of curing agents, which comprises a first curing agent containing sulfur and a second curing agent containing an ester group, whereby it is possible to control the physical properties of the polishing pad as necessary.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; wherein R11 and R12 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R11 and R12 is fluorine, L is a C1-C5 alkylene group or —O—, R13 and R14 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R13 and R14 is fluorine, and n and m are each independently an integer from 0 to 20, with the proviso that n and m are not simultaneously 0.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes in its main chain a silane repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is about 40 or less wherein R11 and R12 are each independently hydrogen or C1-C10 alkyl groups, and n is an integer from 1 to 30.

Abstract: In the composition according to an embodiment, the weight ratio of toluene 2,4-diisocyanate in which one NCO group is reacted and unreacted toluene 2,6-diisocyanate in the urethane-based prepolymer is adjusted, whereby such physical properties as gelation time can be controlled. Thus, the polishing rate and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled while it has a hardness suitable for a soft pad, whereby it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.