Abstract: In a semiconductor laminated structure, a base substrate has a nitride semiconductor crystal plane in an upper surface thereof. A growth blocking film encloses a flow-through pattern which is extended horizontally on the base substrate at a predetermined interval. A nitride semiconductor crystal layer is formed on the base substrate to contact the upper surface thereof between regions of the flow-through pattern and covers the grow blocking film. The semiconductor laminated structure is employed to obtain a nitride semiconductor crystal layer, nitride semiconductor crystal substrate and nitride semiconductor device exhibiting fewer defects and high quality.

Abstract: A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line employing the dummy power line. It is therefore possible to easily change the width of the power lines and to reduce the manufacturing cost and the manufacturing time depending on the formation of the power lines. Furthermore, the power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power lines, if appropriate. Accordingly, mesh of optimized power lines can be provided. Furthermore, more stabilized product characteristics can be secured and the yield of semiconductor memory devices can be enhanced.

Abstract: A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based semiconductor device. The method for manufacturing the nitride based single crystal substrate includes forming a nitride based single crystal layer on a preliminary substrate; forming a polymer support layer by applying a setting adhesive material having flowability on the upper surface of the nitride based single crystal layer and hardening the applied adhesive material; and separating the nitride based single crystal layer from the preliminary substrate by irradiating a laser beam onto the lower surface of the preliminary substrate. The method for manufacturing the nitride based single crystal substrate is applied to the manufacture of a nitride based semiconductor device having a vertical structure.

Abstract: A substrate conveyance device for fabricating a liquid crystal display device is provided. The substrate conveyance device conveys substrates and aligns substrates without using an additional aligning apparatus. The substrate conveyance device includes an arm that forms a body of the substrate conveyance device, a hand and a mover. The hand, that is movable in a first direction, includes a first end coupled with the arm and an upper surface where a substrate is placed on the upper surface. The hand also has a holder which holds a dummy portion which is at an edge of the substrate. The mover is configured to move the hand.

Abstract: There are provided an ultra thin film silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) having a recessed source/drain structure, and a method of fabricating the same.

Abstract: A transistor using impact ionization and a method of manufacturing the same are provided. A gate dielectric layer, a gate, and first and second spacers are formed on a semiconductor substrate. A first impurity layer is formed spaced from the first spacer and a second impurity layer is formed expanding and overlapping with the second spacer therebelow, by performing slant ion-implantation on the semiconductor substrate using the gate and the first and second spacers as a mask. A source and a drain are formed on the semiconductor substrate to be self-aligned with the first and second spacers, respectively, thereby defining an ionization region between the source and the drain in the semiconductor substrate. The source includes a first silicide layer to form a schottky junction with the ionization region.

Abstract: A non-volatile memory device using mobile ionic charges and a method of manufacturing the same are provided. The method includes forming a gate dielectric layer on a semiconductor substrate, injecting mobile ionic charges into the gate dielectric layer by leading source plasma to a surface of the gate dielectric layer and implanting ions within the source plasma into the gate dielectric layer using plasma doping, forming on the gate dielectric layer a gate to which a control voltage controlling distribution of the mobile ionic charges within the gate dielectric layer is supplied to control a threshold voltage, and forming a source region and a drain region in the semiconductor substrate near the gate.

Abstract: Provided is a near-field microscope using a dielectric resonator, which makes it possible to minimize influences by external environments, and to enhance its sensitivity, resolution and function by adjusting the distance between a sample and an apex of a probe. The near-field microscope includes a wave source, a dielectric resonator, a probe, a distance adjusting unit, and a detector. The wave source generates a wave, and a frequency of the wave is adjustable by the wave source. The dielectric resonator propagates the wave from the wave source, and a resonance frequency, impedance, a Q factor and an electromagnetic wave mode of the wave is freely adjustable. The probe scans the wave output from the dielectric resonator on a sample. The distance adjusting unit measures a distance between the probe and the sample and maintains the distance to a predetermined value.

Abstract: A row active control circuit of a PSRAM controls a refresh timing when a refresh operation is performed before activation of a row path for embodiment of a page mode, thereby preventing mis-operations. The row active signal generating unit generates a row active signal when an active condition is set by the internal active signal. The internal active signal generating unit generates the internal active signal in response to a refresh start signal. The row active control unit generates a row active standby signal with the row active signal in response to the internal active signal. The external active signal generates unit for generating an external active control signal in response to the row active standby signal.

Abstract: Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.