Abstract: Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a substrate; an interlayer insulating layer on the substrate; an upper wiring trench in the interlayer insulating layer; an upper wiring layer including an upper wiring barrier layer along a sidewall of the upper wiring trench and a bottom surface of the upper wiring trench, and an upper wiring filling layer on the upper wiring barrier layer, wherein the upper wiring filling layer fills an inside of the upper wiring trench; and a first etching stop layer on each of an upper surface of the interlayer insulating layer and an upper surface of the upper wiring layer, the first etching stop layer including: a first portion in contact with an upper surface of the upper wiring filling layer; a second portion in contact with an upper surface of the upper wiring barrier layer; and a third portion in contact with the upper surface of the interlayer insulating layer, wherein a percentage of nitrogen (N) in the first

Abstract: A semiconductor device includes a substrate; an interlayer insulating layer disposed on the substrate; an upper wiring trench disposed in the interlayer insulating layer; and an upper wiring layer including: an upper wiring barrier layer disposed along a sidewall and a bottom surface of the upper wiring trench, an upper wiring filling layer disposed on the upper wiring barrier layer so as to fill at least a portion of an inside of the upper wiring trench, and an upper wiring capping layer disposed on an upper surface of the upper wiring filling layer, wherein the upper wiring capping layer includes cobalt (Co), and wherein a volume percentage of a crystal structure having a hexagonal close-packed structure included in the upper wiring capping layer is in a range of about 80% to about 100%.

Abstract: A display device includes conductive layers including wires and conductive patterns in a display area and a pad area, a via layer on the conductive layers, a first electrode and a second electrode on the via layer in the display area and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, light emitting elements on the first electrode and the second electrode spaced apart from each other on the first insulating layer, and a first connection electrode on the first electrode and electrically contacting the light emitting elements, and a second connection electrode on the second electrode and electrically contacting the light emitting elements, each of the conductive layers includes a first metal layer and a second metal layer on the first metal layer, and the second metal layer contains copper and has a grain size of about 155 nm or less.

Abstract: A method of manufacturing a composite anode for a lithium ion battery and a composite anode for a lithium ion battery manufactured thereby. According to the method provide herein, since a metal catalyst precursor is reduced using Joule heating to obtain a carbon-metal catalyst composite layer, composite anode for a lithium ion battery having a large area in a short period of time can be provided, which is excellent in terms of economic feasibility. Further, since it is possible to manufacture a composite anode for a lithium ion battery with the improved lithium electrodeposition density and reversibility of lithium ions, a composite anode for a lithium ion battery having high capacity and improved life stability can be obtained.

Abstract: There is provided a semiconductor device including an etching stop film which is placed disposed on a substrate; an interlayer insulating film which is disposed on the etching stop film; a trench which penetrates the interlayer insulating film and the etching stop film; a spacer which extends along side walls of the trench; a barrier film which extends along the spacer and a bottom surface of the trench; and a filling film which fills the trench on the barrier film. The trench includes a first trench and a second trench which are spaced apart from each other in a first direction and have different widths from each other in the first direction. A bottom surface of the second trench is placed disposed below a bottom surface of the first trench.

Abstract: A semiconductor device includes a substrate; a first transistor on the substrate; a first contact on a source/drain pattern of the first transistor; a second transistor on the substrate; a second contact on a gate electrode of the second transistor; a first connecting structure that includes at least one first wiring and at least one first via that are alternately stacked on the first contact; a second connecting structure that includes at least one second wiring and at least one second via that are alternately stacked on the second contact; a first connecting via on the first connecting structure; a second connecting via on the second connecting structure; and a connecting wiring on the first connecting via and the second connecting via.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A semiconductor device including a first interlayer insulating layer on a substrate, a lower wiring pattern in the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, a via filling layer filling a via trench in the second interlayer insulating layer, a third interlayer insulating layer contacting an upper surface of the second interlayer insulating layer, and an upper wiring pattern in an upper wiring trench formed on the via trench in the third interlayer insulating layer and contacting an upper surface of the via filling layer, the upper wiring pattern including a first upper wiring barrier layer on sidewalls of the upper wiring trench, a second upper wiring barrier layer on sidewalls of the first upper wiring barrier layer and the upper surface of the via filling layer, and an upper wiring filling layer on the second upper wiring barrier layer.

Abstract: A for fabricating a semiconductor device comprises forming a mask layer on a substrate, the mask layer defining a through hole that exposes an upper surface of the substrate, the mask layer comprising a first mask layer and a second mask layer, wherein the second mask layer is between the substrate and the first mask layer, and wherein the second mask layer comprises carbon. The method includes forming a liner layer on side walls of the through hole inside the second mask layer.

Abstract: A nonvolatile memory device including a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

Abstract: A semiconductor device includes an interlayer insulating film including a first surface and a second surface opposite to the first surface in a first direction; a source/drain pattern provided in the interlayer insulating film; a channel pattern adjacent to the source/drain pattern in a second direction and contacting the source/drain pattern; a front wiring provided on the first surface of the interlayer insulating film; a back wiring provided on the second surface of the interlayer insulating film; and a first connecting via contact and a second connecting via contact which are provided between the source/drain pattern and the back wiring and connected to the source/drain pattern.

Abstract: A semiconductor device comprising: a lower insulating layer; a field insulating layer on the lower insulating layer; an upper insulating layer on the field insulating layer; a first through via in the upper insulating layer; a second through via in the field insulating layer; and a third through via in the lower insulating layer, wherein the second through via is connected to the first and third through vias, and wherein a width of a top surface of the second through via is greater than a width of a bottom surface of the first through via, a width of a bottom surface of the second through via is greater than a width of a top surface of the third through via, and a width of a middle portion of the second through via is greater than the widths of the top surface and the bottom surface of the second through via.

Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A method for fabricating semiconductor device may include forming a source/drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source/drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source/drain contact on the contact liner. The ion implantation process may include implant impurities into the source/drain pattern. The source/drain contact may be connected to the source/drain pattern.

Abstract: Provided is a semiconductor device including an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern.

Abstract: Semiconductor devices with improved performance and reliability and methods for forming the same are provided. The semiconductor devices include an active pattern extending in a first direction, gate structures spaced apart from each other in the first direction on the active pattern, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner extending along a sidewall of the source/drain contacts. A carbon concentration of the contact liner at a first point of the contact liner is different from a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height.

Abstract: A semiconductor device is provided. The semiconductor device includes a first interlayer insulating layer, a lower wiring disposed inside the first interlayer insulating layer, an etching stop layer which includes first to third layers sequentially stacked on the first interlayer insulating layer, a second interlayer insulating layer disposed on the etching stop layer, and a via which penetrates the second interlayer insulating layer and the etching stop layer, the via is connected to the lower wiring, the via includes a first side wall that is in contact with the second layer, and a second side wall that is in contact with the second interlayer insulating layer, the via includes a first protrusion protruding in a horizontal direction from the first side wall inside the first layer, and a second protrusion protruding in the horizontal direction from the first side wall inside the third layer.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.