Abstract: A semiconductor device comprising: a lower insulating layer; a field insulating layer on the lower insulating layer; an upper insulating layer on the field insulating layer; a first through via in the upper insulating layer; a second through via in the field insulating layer; and a third through via in the lower insulating layer, wherein the second through via is connected to the first and third through vias, and wherein a width of a top surface of the second through via is greater than a width of a bottom surface of the first through via, a width of a bottom surface of the second through via is greater than a width of a top surface of the third through via, and a width of a middle portion of the second through via is greater than the widths of the top surface and the bottom surface of the second through via.

Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.

Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A method for fabricating semiconductor device may include forming a source/drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source/drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source/drain contact on the contact liner. The ion implantation process may include implant impurities into the source/drain pattern. The source/drain contact may be connected to the source/drain pattern.

Abstract: Provided is a semiconductor device including an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern.

Abstract: Semiconductor devices with improved performance and reliability and methods for forming the same are provided. The semiconductor devices include an active pattern extending in a first direction, gate structures spaced apart from each other in the first direction on the active pattern, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner extending along a sidewall of the source/drain contacts. A carbon concentration of the contact liner at a first point of the contact liner is different from a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height.

Abstract: A semiconductor device is provided. The semiconductor device includes a first interlayer insulating layer, a lower wiring disposed inside the first interlayer insulating layer, an etching stop layer which includes first to third layers sequentially stacked on the first interlayer insulating layer, a second interlayer insulating layer disposed on the etching stop layer, and a via which penetrates the second interlayer insulating layer and the etching stop layer, the via is connected to the lower wiring, the via includes a first side wall that is in contact with the second layer, and a second side wall that is in contact with the second interlayer insulating layer, the via includes a first protrusion protruding in a horizontal direction from the first side wall inside the first layer, and a second protrusion protruding in the horizontal direction from the first side wall inside the third layer.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

Abstract: There is provided a semiconductor device including an etching stop film which is placed disposed on a substrate; an interlayer insulating film which is disposed on the etching stop film; a trench which penetrates the interlayer insulating film and the etching stop film; a spacer which extends along side walls of the trench; a barrier film which extends along the spacer and a bottom surface of the trench; and a filling film which fills the trench on the barrier film. The trench includes a first trench and a second trench which are spaced apart from each other in a first direction and have different widths from each other in the first direction. A bottom surface of the second trench is placed disposed below a bottom surface of the first trench.

Abstract: A semiconductor device includes an etching stop film disposed on a substrate; an interlayer insulating film on the etching stop film; a first trench and a second trench which are spaced apart in a first direction, and penetrate the etching stop film and the interlayer insulating film, the first trench having a side wall that exposes the interlayer insulating film, and the second trench having a side wall that exposes the interlayer insulating film; a first spacer which covers the interlayer insulating film exposed by the side wall of the first trench and does not cover a portion of the side wall of the first trench; a second spacer which covers the interlayer insulating film exposed by the side wall of the second trench and does not cover a portion of the side wall of the second trench; a first barrier layer which extends along a side wall of the first spacer, the portion of the side wall of the first trench not covered by the first spacer, and a bottom surface of the first trench; a first filling film which

Abstract: Semiconductor devices having improved performance and reliability. For example, a semiconductor device may include a substrate, an active pattern extending in a first direction, on the substrate, a plurality of gate structures on the active pattern, each including a gate electrode that crosses the active pattern. A lower active contact may be connected to a source/drain pattern. A trench may expose the lower active contact, and a width of a bottom surface of the trench in the first direction may be greater than a width of an upper surface of the lower active contact in the first direction. An etching stop film may be along the bottom surface of the trench and side walls of the trench, and have an uppermost surface coplanar with an upper surface of an upper active contact that extends through the etching stop film and is connected to the lower active contact.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: An etching gas mixture, a method of forming a pattern using the etching gas mixture, and a method of manufacturing an integrated circuit device using the etching gas mixture, the etching gas mixture including a C1-C3 perfluorinated alkyl hypofluorite; and a C1-C10 organosulfur compound that includes a C—S bond in the compound.