Patents by Inventor Joo-sung Kim

Joo-sung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9472624
    Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 18, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Joo-sung Kim, Moon-seung Yang
  • Patent number: 9337381
    Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Young-soo Park, Su-hee Chae
  • Patent number: 9257599
    Abstract: According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Young-soo Park, Young-jo Tak
  • Patent number: 9190270
    Abstract: Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Young-soo Park, Eun-ha Lee
  • Patent number: 9136430
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: September 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Publication number: 20150123140
    Abstract: Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7?k?13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Jun-Youn KIM, Jae-Kyun KIM, Joo-Sung KIM, Young-Soo PARK, Young-Jo TAK
  • Publication number: 20150111369
    Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.
    Type: Application
    Filed: September 12, 2014
    Publication date: April 23, 2015
    Inventors: Jun-youn KIM, Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Young-soo PARK, Su-hee CHAE
  • Publication number: 20150079769
    Abstract: A semiconductor device includes a first coalescent layer, a second coalescent layer, a nitride stacked structure on the second coalescent layer, and a third layer between the first and second coalescent layers. The first coalescent layer includes a plurality of formations that are partially merged, and the third layer is disposed on the formations to allow a first type of stress to be generated in an area which includes the first coalescent layer and a second type of stress to be generated in an area which includes the second coalescent layer.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 19, 2015
    Inventors: Jun-youn KIM, Joo-sung KIM, Young-jo TAK
  • Publication number: 20150060762
    Abstract: According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.
    Type: Application
    Filed: May 28, 2014
    Publication date: March 5, 2015
    Inventors: Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Young-soo PARK, Young-jo TAK
  • Patent number: 8946773
    Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Publication number: 20140353677
    Abstract: Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Young-soo PARK, Eun-ha LEE
  • Patent number: 8890184
    Abstract: A nanostructured light-emitting device including: a first type semiconductor layer; a plurality of nanostructures each including a first type semiconductor nano-core grown in a three-dimensional (3D) shape on the first type semiconductor layer, an active layer formed to surround a surface of the first type semiconductor nano-core, and a second type semiconductor layer formed to surround a surface of the active layer and including indium (In); and at least one flat structure layer including a flat-active layer and a flat-second type semiconductor layer that are sequentially formed on the first type semiconductor layer parallel to the first type semiconductor layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Kim, Taek Kim, Moon-seung Yang
  • Patent number: 8835902
    Abstract: A nano-structured light-emitting device (LED) includes: a plurality of nanostructures on a first type semiconductor layer. Each of the plurality of nanostructures includes: a first type semiconductor nanocore on a portion of the first type semiconductor layer; a current spreading layer formed to cover a surface of the first type semiconductor nanocore and formed of an AlxGa1-xN(0<x<1)/GaN superlattice structure; an active layer on the current spreading layer (or on the first type semiconductor nanocore if the current spreading layer is embedded in the first type semiconductor nanocore); and a second type semiconductor layer on the active layer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Kim, Taek Kim
  • Publication number: 20140061663
    Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 6, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jun-youn KIM, Joo-sung KIM, Moon-seung YANG
  • Publication number: 20140042391
    Abstract: A semiconductor device includes a first coalescent layer, a second coalescent layer, a nitride stacked structure on the second coalescent layer, and a third layer between the first and second coalescent layers. The first coalescent layer includes a plurality of formations that are partially merged, and the third layer is disposed on the formations to allow a first type of stress to be generated in an area which includes the first coalescent layer and a second type of stress to be generated in an area which includes the second coalescent layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 13, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Joo-sung KIM, Young-jo TAK
  • Publication number: 20140042492
    Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Publication number: 20140045284
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Publication number: 20140014990
    Abstract: Lights-emitting device (LED) packages, and methods of manufacturing the same, include at least one light-emitting structure. The at least one light-emitting structure includes a first compound semiconductor layer, an active layer, and a second compound semiconductor layer that are sequentially stacked, at least one first metal layer connected to the first compound semiconductor layer, a second metal layer connected to the second compound semiconductor layer, a substrate having a conductive bonding layer on a first surface of the substrate, and a bonding metal layer configured for eutectic bonding between the at least one first metal layer and the conductive bonding layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Jae-kyun KIM, Joo-sung KIM, Moon-seung YANG, Su-hee CHAE, Young-jo TAK, Hyun-gi HONG
  • Publication number: 20140001438
    Abstract: A semiconductor device includes a buffer structure on a silicon substrate, and at least one gallium nitride-based semiconductor layer on the buffer structure. The buffer structure includes a plurality of nitride semiconductor layers and a plurality of stress control layers that are alternately disposed with the plurality of nitride semiconductor layer. The plurality of stress control layers include a IV-IV group semiconductor material.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 2, 2014
    Inventors: Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI, Young-jo TAK
  • Publication number: 20130334495
    Abstract: A superlattice structure, and a semiconductor device including the same, include a plurality of pairs of layers are in a pattern repeated at least two times, in which a first layer and a second layer constitute a pair, the first layer is formed of AlxInyGa1-x-yN (where 0?x and y?1), the second layer is formed of AlaInbGa1-a-bN (where 0?a, b?1 and x?a), the first and second layers have the same thickness, and a total thickness of each of the plurality of pairs of layers is different than each other.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 19, 2013
    Inventors: Dae-ho LIM, Joo-sung KIM, Jae-kyun KIM, Young-jo TAK