Patents by Inventor Joo-Sung Park

Joo-Sung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8501617
    Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Ae-Ran Hong
  • Patent number: 8395561
    Abstract: The present invention relates to a dual polarization broadband antenna having a single pattern, which is provide with a radiation device having a square structure, in which a plurality of folded dipole elements are formed in a single continuously-connected pattern, and a feeding portion for feeding signals to the plurality of folded dipole elements is formed on the radiation device. Accordingly, the plurality of folded dipole elements formed on the radiation device are connected in a single square and rectangular pattern, so that the structure thereof is simplified, with the result that the cost can be reduced. Furthermore, the feeding portion, that dually feeds signals, and the plurality of folded dipole elements, connected in a single pattern, are coupled, so that the dual polarization characteristic can be easily acquired.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: March 12, 2013
    Assignee: Ace Antenna Corp.
    Inventors: Joo Sung Park, Jae Sun Jin
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Publication number: 20120202336
    Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 9, 2012
    Inventors: Joo-Sung PARK, Se-Myeong Jang, Gil-Sub Kim
  • Patent number: 8198163
    Abstract: A method of fabricating a semiconductor device including forming a plurality of gate structures on a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, forming a dielectric layer on the semiconductor substrate having the gate structures, forming contact holes by etching the dielectric layer to expose parts of the impurity regions at sides of the gate structures, directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and forming conductive plugs in the contact holes.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Park, Se-keun Park
  • Publication number: 20110163394
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Application
    Filed: June 10, 2010
    Publication date: July 7, 2011
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 7948249
    Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: May 24, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-Sung Park
  • Publication number: 20110074453
    Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 31, 2011
    Inventor: Joo-Sung Park
  • Patent number: 7863917
    Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-Sung Park
  • Publication number: 20100304537
    Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 2, 2010
    Inventors: Joo Sung Park, Ae-Ran Hong
  • Patent number: 7795731
    Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Ae-Ran Hong
  • Patent number: 7750432
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Publication number: 20100124808
    Abstract: A method of fabricating a semiconductor device including forming a plurality of gate structures on a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, forming a dielectric layer on the semiconductor substrate having the gate structures, forming contact holes by etching the dielectric layer to expose parts of the impurity regions at sides of the gate structures, directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and forming conductive plugs in the contact holes.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 20, 2010
    Inventors: Joo-sung Park, Se-keun Park
  • Patent number: 7589603
    Abstract: Disclosed is a phase shifter having a power dividing function. The phase shifter includes: an input port for receiving a radio frequency (RF) signal; a power dividing unit for dividing the RF signal into a first divided signal of which phase is to be varied and a second divided signal having a fixed phase value; a first output port for outputting the second divided signal having the fixed phase value; a phase shift unit for dividing the first divided signal into a third divided signal and a fourth divided signal wherein the third divided signal and the fourth divided signal move in opposite directions; a phase delay unit for shifting phase of the third divided signal and the fourth divided signal based on a difference in a path length of the third divided signal and the fourth divided signal, to thereby generate phase-shifted signals; and at least two second output ports connected to the phase delay unit, for outputting the phase-shifted signals.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: September 15, 2009
    Assignee: Ace Technology
    Inventors: Jae-Hoon Tae, Yong-Ju Lee, Myoung-Kuk Kim, Joo-Sung Park, Joo-Hyung Lee
  • Patent number: 7573142
    Abstract: An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: August 11, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Han Park, Joo-Sung Park, Dong-Hyun Han
  • Publication number: 20090179814
    Abstract: The present invention relates to a dual polarization broadband antenna having a single pattern, which is provide with a radiation device having a square structure, in which a plurality of folded dipole elements are formed in a single continuously-connected pattern, and a feeding portion for feeding signals to the plurality of folded dipole elements is formed on the radiation device. Accordingly, the plurality of folded dipole elements formed on the radiation device are connected in a single square and rectangular pattern, so that the structure thereof is simplified, with the result that the cost can be reduced. Furthermore, the feeding portion, that dually feeds signals, and the plurality of folded dipole elements, connected in a single pattern, are coupled, so that the dual polarization characteristic can be easily acquired.
    Type: Application
    Filed: April 2, 2007
    Publication date: July 16, 2009
    Applicant: ACE ANTENNA CORP.
    Inventors: Joo Sung Park, Jae Sun Jin
  • Publication number: 20090014829
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Application
    Filed: September 12, 2008
    Publication date: January 15, 2009
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 7442613
    Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Jae Hur, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 7439102
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 7385242
    Abstract: A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: June 10, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Sung Lee, Joo-Sung Park