Abstract: A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

Abstract: Methods may be provided to determine an alignment of a laser with respect to an integrated circuit device including a fuse pattern and a monitoring pattern adjacent the fuse pattern. More particularly, the fuse pattern may be cut with radiation from the laser. After cutting the fuse pattern, an electrical signal through the monitoring pattern may be measured to determine an alignment of radiation from the laser with respect to the fuse pattern. Related structures, devices, and circuits are also discussed.

Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: A method of fabricating a semiconductor device includes forming a photo-sensitive polyimide layer on a semiconductor substrate, patterning the photo-sensitive polyimide layer using a mask having a layer for adjusting light transmittance, and forming an epoxy molding compound on the substrate having the photo-sensitive polyimide layer patterns.

Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

Abstract: An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.

Abstract: Disclosed is a phase shifter having a power dividing function. The phase shifter includes: an input port for receiving a radio frequency (RF) signal; a power dividing unit for dividing the RF signal into a first divided signal of which phase is to be varied and a second divided signal having a fixed phase value; a first output port for outputting the second divided signal having the fixed phase value; a phase shift unit for dividing the first divided signal into a third divided signal and a fourth divided signal wherein the third divided signal and the fourth divided signal move in opposite directions; a phase delay unit for shifting phase of the third divided signal and the fourth divided signal based on a difference in a path length of the third divided signal and the fourth divided signal, to thereby generate phase-shifted signals; and at least two second output ports connected to the phase delay unit, for outputting the phase-shifted signals.

Abstract: A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

Abstract: A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

Abstract: A semiconductor device and methods of fabricating the semiconductor device, suitable for preventing electrical bridges between storage nodes without the increase of planar areas. In one embodiment, a semiconductor device comprises a semiconductor substrate and at least one storage node formed over the semiconductor substrate. The storage node has a bottom portion and a sidewall extending upward from a rim of the bottom portion. At least a portion of the sidewall is recessed.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

Abstract: A method of constructing a multi-layered wiring system of a semiconductor device is provided, wherein the method includes steps of: sequentially forming first and second conductive layers on a semiconductor unit board having the first insulation layer; forming an anti-reflective layer in a structure of Ti/TiN deposition layers by means of a sputter device having a collimator on the second conductive layer; selectively etching predetermined portions of the anti-reflective layer, the second conductive layer and the first conductive layer to expose predetermined portions of the first insulation layer to form a metal wire; forming the second insulation layer at the front side of the aforementioned structure; forming a via hole by dry-etching predetermined portions of the second insulation layer and the anti-reflective layer to expose predetermined portions on the surface of the metal wire with tapered parts of anti-reflective layer remaining along the edges of the bottom thereof; performing a wet etching process