Abstract: A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Abstract: Disclosed is a method of removing residual enzymes when microencapsulating enzymes, and more particularly, for inactivating enzymes remaining in an uncapsulated form during microencapsulation of enzymes by treating dispersion fluid of microcapsules containing enzymes with ozone, together with removal of microorganisms harmful to human beings, where the ozone treatment is conducted for 1–10 min with 1–10 ppm of ozone generated from a UV lamp in a range from 150 to 200 nm wavelength.

Abstract: A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diffusion barrier on the etch stop layer, forming a via hole exposing the etch stop layer by etching the second diffusion barrier, the second interlayer insulating layer, the first diffusion barrier, and the first interlayer insulating layer, forming a first trench overlapping the via hole by etching the second diffusion barrier and the second interlayer insulating layer, forming a second trench continuous to the first trench by etching the first diffusion barrier and part of the first interlayer insulating layer, and removing the etch stop layer exposed through the via hole, wherein the first and second trenches are etched under different dry etching conditions.

Abstract: An increase in parasitic capacitance between lines, an increase of contact resistance, and corrosion of a metal line may be effectively reduced or prevented when a semiconductor device is manufactured by a method including forming an interlayer insulating layer including a low-k dielectric material on a semiconductor substrate having a structure thereon, etching the interlayer insulating layer to form a hole and expose a portion of the structure, and cleaning the hole using an inorganic cleaning agent.

Abstract: Contact resistance of a semiconductor device may be reduced, and thereby the reliability of the semiconductor device may be enhanced, when a metal line is formed in a semiconductor device according to a method including: (i) forming a metal layer on a semiconductor substrate; (ii) forming a groove on an upper surface of the metal layer by etching the metal layer; (iii) etching the metal layer so as to form a groove-engraved lower metal line that is wider than the groove; (iv) forming an insulator layer covering the semiconductor substrate and the groove-engraved lower metal line; (v) etching the insulator layer so as to form a contact hole exposing the groove; and (vi) forming a contact electrode filling the contact hole and an upper metal line connected thereto, above the insulator layer.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected, forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film, and forming a trench having a width wider than that of the via hole on the intermetal insulating film. The method also includes the steps of exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source, performing a nitrogen passivation process for the exposed lower metal film, and forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

Abstract: Methods for fabricating semiconductor devices are disclosed. A disclosed method for fabricating a semiconductor device comprises: forming a film on a semiconductor substrate; forming a photoresist pattern on the film; etching the photoresist pattern by chemical dry etching (CDE) to reduce a width of the photoresist pattern; and etching an exposed portion of the film using the photoresist pattern as a mask.

Abstract: A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Abstract: Disclosed is a method of removing residual enzymes when microencapsulating enzymes, and more particularly, for inactivating enzymes remaining in an uncapsulated form during microencapsulation of enzymes by treating dispersion fluid of microcapsules containing enzymes with ozone, together with removal of microorganisms harmful to human beings, where the ozone treatment is conducted for 1-10 min with 1-10 ppm of ozone generated from a UV lamp in a range from 150 to 200 nm wavelength.