Abstract: A method of transmitting data more effectively, and more particularly, a method of transmitting data to a group comprising a plurality of reception stations that receive the same data from a transmission station when the stations communicate the data in a power line communication (PLC) network, and an apparatus to do the same. According to the method, a transmission station transmits data to a group including a plurality of reception stations that receive the same data at a time, to prevent a channel bandwidth from being wasted, and to prevent a station that does not desire to receive the data from receiving the data.

Abstract: A method and apparatus are provided for transmitting data more efficiently between stations in a power line communication (PLC) network while preventing a hidden node problem. The method of transmitting data includes: detecting a hidden node in a network; and transmitting at least one of a request to send (RTS) command and a clear to send command (CTS) to the network before transmitting the data, if a hidden node is detected and a transmitting station a data packet having a size which is larger than a predetermined size. Using the method, interference of data transmissions and a low data throughput caused by the hidden node problem should be prevented.

Abstract: A method of transmitting data more effectively, and more particularly, a method of classifying service traffic, transmitting data according to the classifications of the service traffic, and performing a contention free slot (CFS) allocation in order to transmit data in a power line communication (PLC) network, and an apparatus to do the same. The data transmission method includes determining transmission priority of data according to service traffic characteristics, and transmitting data according to the determined transmission priority, thereby providing differentiated quality of service (QoS) according to service traffic characteristics.

Abstract: A method of data communication between power line communication (PLC) stations belonging to different PLC cells includes transmitting a station ID of a PLC reception station to a PLC cell bridge (CB) of a first PLC cell to which a PLC transmission station belongs, receiving a group identification (GID) and an encryption key of a second PLC cell to which the PLC reception station belongs from the PLC CB of the first PLC cell, encrypting data to be transmitted using the encryption key of the second PLC cell, and transmitting the station ID of the PLC reception station, the GID of the second PLC cell, and the encrypted data, to the PLC CB of the first PLC cell, and an apparatus to perform the method.

Abstract: Disclosed are an insulated electric wire with partial discharge resistance and a composition for manufacturing the same. The insulated electric wire with partial discharge resistance according to the present invention includes an insulating base resin constituting a basic material of an insulated electric wire; an inorganic insulator included at a content of 5 to 40 parts by weight on the basis of 100 parts by weight of the insulating base resin; and a rubbery modifier included at a content of 0.1 to 30 parts by weight on the basis of 100 parts by weight of the insulating base resin to improve flexibility of an insulated electric wire. The insulated electric wire with partial discharge resistance of the present invention may be useful to prevent occurrence of cracks caused by winding of an insulated electric wire since the insulated electric wire has a sufficient partial discharge resistance and also enhances sufficient physical properties such as flexibility, pliability, bendability, elongation, etc.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

Abstract: Provided is an apparatus and method of displaying power line communication channel information. The apparatus for displaying power line communication (PLC) channel information includes a channel information determining unit which performs PLC channel estimation and determines channel information including a bandwidth which is available for a user in a power line communication network; and a channel information displaying unit which displays the channel information to the user. Since channel information is determined through channel estimation and displayed to a user, it is possible to easily check whether a channel can be used before installing a power line communication (PLC) device. In an application, information on kinds of a service which can be selected by the user or expected quality of the service can be previously checked.

Abstract: Provided is an apparatus for adjusting the phase difference between different phases in a power line communication (PLC) system. The apparatus includes a power signal blocking unit blocking a power signal and allowing a data signal to pass between two different phases on three-phase power lines; and a data signal delaying unit delaying the data signal by the phase difference between the two different phases. Accordingly, it is possible to prevent data collision and a time delay in data transmission between different phases by employing the phase adjusting apparatus in a PLC system, thereby improving the performance of PLC.

Abstract: A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

Abstract: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

Abstract: A power line communication (PLC) method includes determining whether a destination communication apparatus to receive a data packet can directly communicate without using a repeater, transmitting the data packet to the destination communication apparatus when the destination communication apparatus can directly communicate without using the repeater, and transmitting the data packet to the repeater when the destination communication apparatus cannot directly communicate without using the repeater, and a power line communication (PLC) apparatus to perform the method.

Abstract: A transmitter having a vertical BJT, capable of reducing power consumption, carrier leakage of a local oscillator and an error vector magnitude (EVM), is disclosed. In the transmitter, vertical BJTs implemented by a standard triplex well CMOS process are used in a frequency up-mixer and a baseband analog circuit including a DAC, an LPF, a VGA and a PGA, thereby improving the overall performance of the transmitter.

Abstract: A memory module and a memory system are provided. The memory module includes a first circuit board on which at least one memory chip is mounted, a second circuit board on which at least one memory chip is mounted, and a flexible coupler electrically connecting the first circuit board to the second circuit board. The memory module is bendable and is configured to extend around a memory controller. The memory chips are electrically coupled with the memory controller via a respective plurality of signal lines. The bendable memory module is configured to be bent around the memory controller such that respective lengths of the signal lines are equal.

Abstract: A network relay apparatus and method are provided. The network relay includes a sub-network interface for communication with a sub-network, a plurality of backbone network interfaces for communication with a plurality of backbone networks, and a control unit for outputting data, which is received from a device included in the sub-network through the sub-network interface, through one of the backbone network interfaces. In the network relay, it is possible to fulfill various requests for communication quality by connecting the sub-network with the plurality of backbone networks.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract: A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.

Abstract: A wireless network device and a communication method using the wireless network device are provided to simplify an association process of the device moving over different wireless networks and to enhance mobility of the device. The wireless network device includes an allocater allocating a device identifier (ID) to a predetermined device, an information generator generating information on the allocated device ID, and a first controller generating a packet containing the generated device ID and transmitting the generated packet to another wireless network.

Abstract: A wireless network device and a method for reassociation between wireless networks using the wireless network device designed to simplify a reassociation process of the device moving between the wireless networks are provided. The wireless network device includes a first frame transceiver receiving a reassociation request frame from a predetermined device, a device identifier (ID) extractor extracting a device ID from the reassociation request frame, and a first controller determining a reassociation process of the device that has sent the reassociation request frame according to the extracted device ID.

Abstract: Methods of forming a semiconductor device can include forming a first conductive layer of a gate electrode on a substrate of a device and forming a second conductive layer of a resistor, that is different than the first conductive layer, on the substrate spaced-apart from the gate electrode. Related devices are also disclosed.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.