Patents by Inventor Joon-Hee Lee

Joon-Hee Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7450597
    Abstract: A wireless network device and a method for reassociation between wireless networks using the wireless network device designed to simplify a reassociation process of the device moving between the wireless networks are provided. The wireless network device includes a first frame transceiver receiving a reassociation request frame from a predetermined device, a device identifier (ID) extractor extracting a device ID from the reassociation request frame, and a first controller determining a reassociation process of the device that has sent the reassociation request frame according to the extracted device ID.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-hee Lee, Seung-seop Shim
  • Publication number: 20080268218
    Abstract: The present invention relates to an insulated electric wire. The insulated electric wire according to the present invention includes a high adhesion resin layer made of a polyamideimide resin containing a compound having a polar group in a molecular structure of an insulation material; and a high flexibility resin layer provided on the high adhesion resin layer. The present invention advantageously improves adherence between a polyamideimide resin and a conductor, and provides adhesive strength with the conductor to improve flexibility of the insulated electric wire and at the same time to improve flexibility of an insulator without deterioration of heat resistance of the insulator.
    Type: Application
    Filed: November 19, 2007
    Publication date: October 30, 2008
    Inventor: Joon-Hee Lee
  • Patent number: 7441167
    Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Cheul Kim, Hee-Joo Choi, Kae-Won Ha, Joon-Hee Lee
  • Publication number: 20080237679
    Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
    Type: Application
    Filed: June 4, 2008
    Publication date: October 2, 2008
    Inventors: Jong-Sun Sel, Jung-Dal Choi, Joon-Hee Lee, Hwa-Kyung Shin
  • Patent number: 7421558
    Abstract: A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-joo Choi, Joon-hee Lee, Dong-jun Kim
  • Patent number: 7417998
    Abstract: A wireless network device and a communication method using the wireless network device are provided to simplify an association process of the device moving over different wireless networks and to enhance mobility of the device. The wireless network device includes an allocater allocating a device identifier (ID) to a predetermined device, an information generator generating information on the allocated device ID, and a first controller generating a packet containing the generated device ID and transmitting the generated packet to another wireless network.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joon-hee Lee
  • Patent number: 7414202
    Abstract: Disclosed are an insulated electric wire with partial discharge resistance and a composition for manufacturing the same. The insulated electric wire with partial discharge resistance according to the present invention includes an insulating base resin constituting a basic material of an insulated electric wire; an inorganic insulator included at a content of 5 to 40 parts by weight on the basis of 100 parts by weight of the insulating base resin; and a rubbery modifier included at a content of 0.1 to 30 parts by weight on the basis of 100 parts by weight of the insulating base resin to improve flexibility of an insulated electric wire. The insulated electric wire with partial discharge resistance of the present invention may be useful to prevent occurrence of cracks caused by winding of an insulated electric wire since the insulated electric wire has a sufficient partial discharge resistance and also enhances sufficient physical properties such as flexibility, pliability, bendability, elongation, etc.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: August 19, 2008
    Assignee: LS Cable Ltd.
    Inventors: Joon-Hee Lee, Ki-Hong Park
  • Publication number: 20080175081
    Abstract: A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 24, 2008
    Inventors: Byoung-Sul Kim, Joon Hee Lee, Jae In Song, Jun-Ho Jo
  • Publication number: 20080176072
    Abstract: Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin, presented in the Chemistry FIG. 1; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost insulated coating layer contacted with the conducting wire, shows the increased adhesivity of the insulated coating layer to the conducting wire without forming an additional bonding layer, as well as the excellent physical properties such as the wear resistance and flexibility, etc.
    Type: Application
    Filed: May 27, 2005
    Publication date: July 24, 2008
    Inventor: Joon-Hee Lee
  • Patent number: 7397093
    Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Sun Sel, Jung-Dal Choi, Joon-Hee Lee, Hwa-Kyung Shin
  • Patent number: 7394696
    Abstract: A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronics Co.
    Inventors: Joon-Hee Lee, Su-In Baek
  • Publication number: 20080093678
    Abstract: A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.
    Type: Application
    Filed: December 27, 2006
    Publication date: April 24, 2008
    Inventors: Joon-Hee Lee, Su-In Baek
  • Publication number: 20080005631
    Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.
    Type: Application
    Filed: June 11, 2007
    Publication date: January 3, 2008
    Inventors: Youn-Cheul Kim, Hee-Joo Choi, Kae-Won Ha, Joon-Hee Lee
  • Publication number: 20070264951
    Abstract: A PLL includes an open-loop automatic frequency calibration circuit. The open-loop automatic frequency calibration circuit includes a frequency detector, first and second sinks, a comparator and a bank selector. The frequency detector generates an up-signal and a down-signal responding to a frequency difference between a first phase difference signal having a phase difference from a reference oscillation signal and the second phase difference signal having a phase difference from a frequency division oscillation signal. The first and second sinks discharge the first and second capacitors respectively responding to the up-signal and the down-signal. The comparator compares voltages of the first and second capacitors. The bank selector selects a bank according to binary search, selects an optimum bank among two banks lastly searched, and outputs a bank selection signal. The voltage-controlled oscillation changes frequency features thereof in response to the bank selection signal.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 15, 2007
    Inventors: Seong-Hwan Cho, Kyung-Lok Kim, Jung-Hyup Lee, Joon-Hee Lee
  • Publication number: 20070242745
    Abstract: A method and apparatus to efficiently transmit data. The method and apparatus effectively aggregate data and transmit the data in a high-speed power line communication (PLC) network. The method of transmitting the data includes combining each of at least one or more data units transferred from an upper layer, with a field to indicate attribute information of the data unit, dividing the combined data units and fields into frame blocks of an identical size, and aggregating the divided frame blocks and transferring the aggregated frame blocks as one frame to a PHY layer. In this way, data units of a variety of types and sizes transferred from the upper layer are aggregated and transmitted as the one frame.
    Type: Application
    Filed: December 22, 2006
    Publication date: October 18, 2007
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Jun-hae Choi, Seung-gi Chang, Chang-yeul Kwon, Joon-hee Lee, Jun-han Lee
  • Publication number: 20070230497
    Abstract: A method of negotiating channel sharing between adjacent cells when there are a plurality of cells in a power line communication (PLC) network. The method includes attempting to negotiate the channel sharing during a minimum contention access period (CAP) which starts after a maximum beacon period ends and ends before a CAP of each PLC cell ends, wherein the maximum beacon period indicates a maximum size that a beacon frame in a super-frame transmitted from a coordinator of each PLC cell can have. When an attempt to negotiate the channel sharing is made using this method, interference does not occur during channel sharing negotiation, and effective channel sharing can be achieved, thereby eliminating interference between adjacent cells.
    Type: Application
    Filed: February 13, 2007
    Publication date: October 4, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-hae Choi, Joon-hee Lee, Ju-han Lee, Hyun-ah Sung, In-hwan Kim, Ho-Jeong You
  • Publication number: 20070230331
    Abstract: A power line communication (PLC) network and method, in which a coordinator can be changed. The PLC network includes a coordinator and a standby coordinator. The coordinator performs scheduling coordination in a PLC cell and periodically transmits scheduling information about the scheduling coordination to stations in the PLC cell. The standby coordinator serves as the new coordinator instead of the coordinator when the coordinator does not operate for a predetermined amount of time.
    Type: Application
    Filed: December 19, 2006
    Publication date: October 4, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joon-hee Lee, Ju-han Lee, Jun-hae Choi
  • Patent number: 7274317
    Abstract: A transmitter having a vertical BJT, capable of reducing power consumption, carrier leakage of a local oscillator and an error vector magnitude (EVM), is disclosed. In the transmitter, vertical BJTs implemented by a standard triplex well CMOS process are used in a frequency up-mixer and a baseband analog circuit including a DAC, an LPF, a VGA and a PGA, thereby improving the overall performance of the transmitter.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: September 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-seong Eo, Il-ku Nam, Sung-jae Jung, Kwy-ro Lee, Heung-bae Lee, Kyu-don Choi, Joon-hee Lee
  • Publication number: 20070218921
    Abstract: A method of joining a cell by using a proxy coordinator. The method of joining a cell by using a proxy coordinator includes requesting a second device to operate as a proxy coordinator from a first device positioned out of a beacon frame reachable area of the cell, transmitting a time period to operate as the proxy coordinator allocated by a coordinator of the cell, informing the first device that the second device can operate as the proxy coordinator, transmitting a cell join request to the proxy coordinator from the first device through the second device, and transmitting a beacon frame including time allocation information from the coordinator to the first device through the second device.
    Type: Application
    Filed: January 3, 2007
    Publication date: September 20, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ju-han Lee, Joon-hee Lee, Jun-hae Choi, Hyun-ah Sung, In-hwan Kim, Seung-gi Chang
  • Publication number: 20070220088
    Abstract: A method of distributing group identifiers IDs (GIDs) in a power line communication (PLC) network, a method of receiving the GIDs, an authentication apparatus, and a PLC apparatus are provided. The authentication apparatus includes: an authentication mode storing unit which stores an authentication mode having a value including one of an authentication authorized mode and an authentication unauthorized mode; a GID request receiver which receives a GID request message from a PLC apparatus; and a GID transmitter which, if the authentication mode is the authentication authorized mode, transmits a GID corresponding to the PLC apparatus to the PLC apparatus. Authentication is realized in a PLC media access control layer distributing the GIDs between a PLC apparatus and an authentication apparatus, so manually inputting a GID into the PLC apparatus is not necessary. Further, the GIDs are distributed via the authentication apparatus, thereby centrally managing the GIDs.
    Type: Application
    Filed: October 24, 2006
    Publication date: September 20, 2007
    Inventors: Jun-hae Choi, In-hwan Kim, Seung-gi Chang, Joon-hee Lee, Ju-han Lee, Ji-hoon Kim, Ho-jeong You