Patents by Inventor Joon Sang Park

Joon Sang Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7781281
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Young Kim, Chang-Ki Hong, Bo-Un Yoon, Joon-Sang Park
  • Publication number: 20100144135
    Abstract: A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 10, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Kwon, Young-Soo Lim, Sung-Un Kwon, Yong-Ho Ha, Jeong-Hee Park, Joon-Sang Park, Myung-Jin Kang, Doo-Hwan Park
  • Publication number: 20100124817
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Application
    Filed: January 27, 2010
    Publication date: May 20, 2010
    Inventors: Ho-Young KIM, Chang-Ki HONG, Bo-Un YOON, Joon-Sang PARK
  • Patent number: 7670942
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Grant
    Filed: September 23, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Young Kim, Chang-Ki Hong, Bo-Un Yoon, Joon-Sang Park
  • Patent number: 7612359
    Abstract: A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: November 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Yoon-Ho Son, Sung-Lae Cho, Joon-Sang Park
  • Publication number: 20090243117
    Abstract: A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventors: Jeong-Hee Park, Yong-Ho Ha, Hyeong-Geun An, Joon-Sang Park, Hyun-Suk Kwon, Myung-Jin Kang, Doo-Hwan Park
  • Patent number: 7531456
    Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Se-Rah Yun, Chang-Ki Hong, Bo-Un Yoon, Jae-Kwang Choi, Joon-Sang Park
  • Publication number: 20090017577
    Abstract: Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 15, 2009
    Inventors: Hyeong-Geun An, Dong-Ho Ahn, Young-Soo Lim, Yong-Ho Ha, Jun-Young Jang, Dong-Won Lim, Gyeo-Re Lee, Joon-Sang Park, Han-Bong Ko, Young-Lim Park
  • Publication number: 20080230762
    Abstract: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.
    Type: Application
    Filed: May 1, 2008
    Publication date: September 25, 2008
    Inventors: Joon-sang Park, Chang-ki Hong, Sang-yong Kim
  • Patent number: 7384825
    Abstract: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 10, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-sang Park, Chang-ki Hong, Sang-yong Kim
  • Publication number: 20080081460
    Abstract: In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary insulating layer pattern including a central portion and a peripheral portion on the substrate. The peripheral portion of the photoresist pattern is higher than that of the central portion of the preliminary insulating layer pattern. The preliminary insulating layer pattern is polished to form a planarized insulating layer on the substrate.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 3, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang-Yeon Yoo, Chung-Ki Min, Yung-Jun Kim, Joon-Sang Park, Dong-Keun Kim, Tae-Eun Kim
  • Publication number: 20080011999
    Abstract: A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug.
    Type: Application
    Filed: September 25, 2007
    Publication date: January 17, 2008
    Inventors: Suk-Hun Choi, Yoon-Ho Son, Sung-Lae Cho, Joon-Sang Park
  • Publication number: 20070284743
    Abstract: A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.
    Type: Application
    Filed: August 1, 2007
    Publication date: December 13, 2007
    Inventors: Suk-Hun Choi, Yoon-Ho Son, Sung-Lae Cho, Joon-Sang Park
  • Patent number: 7291556
    Abstract: A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: November 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Yoon-Ho Son, Sung-Lae Cho, Joon-Sang Park
  • Patent number: 7265050
    Abstract: A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: September 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Yoon-Ho Son, Sung-Lae Cho, Joon-Sang Park
  • Publication number: 20070148968
    Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.
    Type: Application
    Filed: November 21, 2006
    Publication date: June 28, 2007
    Inventors: Byoung-Ho Kwon, Se-Rah Yun, Chang-Ki Hong, Bo-Un Yoon, Jae-Kwang Choi, Joon-Sang Park
  • Publication number: 20070145012
    Abstract: Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.
    Type: Application
    Filed: October 4, 2006
    Publication date: June 28, 2007
    Inventors: Joon-Sang Park, Jong-Won Lee, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Publication number: 20070072407
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Application
    Filed: September 23, 2006
    Publication date: March 29, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-Young Kim, Chang-Ki Hong, Bo-Un Yoon, Joon-Sang Park
  • Patent number: 7097545
    Abstract: Chemical mechanical apparatuses including a polishing pad conditioning unit for improving a conditioning rate and wear uniformity of a polishing pad are provided. In one aspect, a chemical mechanical polishing apparatus includes a polishing pad conditioner including conditioning disks disposed in a radial direction of a planarizing surface of a circular polishing pad and contacted with the planarizing surface of the circular polishing pad during rotation of the circular polishing pad. The conditioning disks are connected to first drive units supported by an arm disposed over the circular polishing pad and extended in a radial direction of a planarizing surface of the circular polishing pad. The arm is connected to second drive units. The second drive units move the arm horizontally and reciprocally in the radial direction of the planarizing surface of the circular polishing pad. Thus, a conditioning rate and wear uniformity of the polishing pad may be improved.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: August 29, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Won Lee, Joon-Sang Park, Chang-Ki Hong
  • Publication number: 20050227496
    Abstract: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 13, 2005
    Inventors: Joon-sang Park, Chang-ki Hong, Sang-yong Kim