Patents by Inventor Joon-soo Park

Joon-soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136328
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Joon Young Park, Jung Soo Park, Ji Hye Yoon
  • Publication number: 20240130261
    Abstract: Disclosed herein is a frame apparatus for an agricultural work vehicle. The frame apparatus includes: an engine frame configured to support the engine of an agricultural work vehicle; a front frame connected to each of a front work machine and the engine frame to support the front work machine mounted in front of the agricultural work vehicle; a center case spaced apart from the front frame based on a first axis direction, and disposed behind the engine frame; a rear axle case coupled to the rear of the center case; side frames each coupled to each of the front frame and the rear axle case on both sides of the agricultural work vehicle; and a crossbar coupled to the side frames while connecting the side frames on both sides based on a second axis direction perpendicular to the first axis direction.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 25, 2024
    Inventors: Ji Soo PARK, Hyo Jong CHON, Han Yeol YU, Joon Hyung KIM
  • Patent number: 11957669
    Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 16, 2024
    Assignee: AMOREPACIFIC CORPORATION
    Inventors: Joon Ho Choi, Won Kyung Cho, Kwang-Hyun Shin, Byoung Young Woo, Ki-Wha Lee, Min-Soo Kim, Jong Hwa Roh, Mi Young Park, Young-Ho Park, Eun Sil Park, Jae Hong Park
  • Publication number: 20240090318
    Abstract: The present invention relates to a novel heterocyclic compound usable in an organic light-emitting device and to an organic light-emitting device comprising same, wherein [chemical formula A] is as described in the detailed description of the invention.
    Type: Application
    Filed: December 28, 2021
    Publication date: March 14, 2024
    Inventors: Se-Jin LEE, Seok-Bae PARK, Si-In KIM, Hee-Dae KIM, Yeong-Tae CHOI, Ji-Yung KIM, Kyung-Tae KIM, Myeong-Jun KIM, Kyeong-hyeon KIM, Seung-soo LEE, Tae Gyun LEE, Joon-Ho KIM
  • Publication number: 20240088453
    Abstract: Disclosed herein relates to an electrode for a lithium secondary battery and a manufacturing method thereof, and since the electrode for a lithium secondary battery is provided with an auxiliary coating layer containing inorganic particles, a phenolic compound, and a binder at the end of an electrode mixture layer containing an electrode active material, thereby improving energy density of the battery due to an improvement in thickness deviation at the end of the electrode mixture layer, and preventing lithium from being precipitated at the end of the electrode, especially the negative electrode, due to increase in the adhesive strength of the separator at the end of the electrode, it has an advantage of excellent safety.
    Type: Application
    Filed: December 22, 2022
    Publication date: March 14, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Joon Sun PARK, Taek Soo LEE, Man Hyeong KIM, Min Hyuck CHOI, Guk Tae KIM
  • Patent number: 11473079
    Abstract: The present invention relates to a method for prenatal diagnosis using digital PCR, and more particularly to a method for providing information for diagnosis of chromosomal aneuploidy in a fetus, comprising: (a) extracting DNAs from pregnant woman's blood; (b) classifying the DNAs according to size to obtain DNAs having a size of 1,000 bp or less; (c) performing digital PCR using the obtained DNAs of step (b), for a control gene located on a chromosome not associated with chromosomal aneuploidy and a target gene located on a chromosome associated with chromosomal aneuploidy; (d) calculating a ratio of a quantitative digital PCR value of the target gene to a quantitative digital PCR value of the control gene; and (e) determining that when the ratio calculated in step (d) is 0.70-1.14, a chromosome number of the fetus is normal.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 18, 2022
    Assignee: BIOCORE CO., LTD.
    Inventors: Seung Yong Hwang, Moon Ju Oh, Seung Jun Kim, Jong Pil Youn, Ji Hoon Kim, Seung Yong Lee, Jeong Jin Ahn, Joon Soo Park, Hyo Jung Choi
  • Publication number: 20220118308
    Abstract: According to the present disclosure, provided is a hip-up exercise apparatus. The hip-up exercise apparatus includes a frame defining an opening at one side thereof and fixing holes at both sides of upper surfaces thereof; a footrest portion disposed at the opening of the frame; a pair of pillars inserted into and coupled to the fixing holes of the frame; and a back supporter connecting upper portions of the pair of pillars and configured to support a back; and the pillars are separated from the fixing holes, are rotated downward, and are turned over, to attach rear surfaces of the pillars to upper surfaces of the frame.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 21, 2022
    Inventor: Joon-soo Park
  • Patent number: 10553438
    Abstract: A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Kyeong Jang, Sang Jin Kim, Dong Woon Park, Joon Soo Park, Chang Jae Yang, Kwang Sub Yoon, Hye Kyoung Jue
  • Patent number: 10276373
    Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Chul Jeong, Tae Kyu Lee, Sung Sik Park, Joon Soo Park, Kwang Sub Yoon, Boo Hyun Ham
  • Publication number: 20190100749
    Abstract: The present invention relates to a method for prenatal diagnosis using digital PCR, and more particularly to a method for providing information for diagnosis of chromosomal aneuploidy in a fetus, comprising: (a) extracting DNAs from pregnant woman's blood; (b) classifying the DNAs according to size to obtain DNAs having a size of 1,000 bp or less; (c) performing digital PCR using the obtained DNAs of step (b), for a control gene located on a chromosome not associated with chromosomal aneuploidy and a target gene located on a chromosome associated with chromosomal aneuploidy; (d) calculating a ratio of a quantitative digital PCR value of the target gene to a quantitative digital PCR value of the control gene; and (e) determining that when the ratio calculated in step (d) is 0.70-1.14, a chromosome number of the fetus is normal.
    Type: Application
    Filed: October 28, 2016
    Publication date: April 4, 2019
    Inventors: Seung Yong Hwang, Moon Ju Oh, Seung Jun Kim, Jong Pil Youn, Ji Hoon Kim, Seung Yong Lee, Jeong Jin Ahn, Joon Soo Park, Hyo Jung Choi
  • Publication number: 20180096840
    Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.
    Type: Application
    Filed: April 19, 2017
    Publication date: April 5, 2018
    Inventors: Yong Chul JEONG, Tae Kyu LEE, Sung Sik PARK, Joon Soo PARK, Kwang Sub YOON, Boo Hyun HAM
  • Publication number: 20170372906
    Abstract: A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate.
    Type: Application
    Filed: January 19, 2017
    Publication date: December 28, 2017
    Inventors: Yun Kyeong JANG, Sang Jin KIM, Dong Woon PARK, Joon Soo PARK, Chang Jae YANG, Kwang Sub YOON, Hye Kyoung JUE
  • Publication number: 20150309411
    Abstract: Methods of forming a pattern are provided. The methods may include forming a dual tone photoresist layer on a support layer, forming a low light exposure region, a middle light exposure region, and a high light exposure region in a first region of the dual tone photoresist layer and forming a low light exposure region and a middle light exposure region in a second region of the dual tone photoresist layer by exposing the dual tone photoresist layer to light by using a mask comprising a gray feature. The method may also include forming preliminary patterns in the first region by performing a positive development process and forming first patterns which are spaced apart from one another in the first region and second patterns which are spaced apart from one another in the second region by performing a negative development process.
    Type: Application
    Filed: April 6, 2015
    Publication date: October 29, 2015
    Inventors: Sung-wook HWANG, Soon-mok HA, Joon-soo PARK
  • Patent number: 8785319
    Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Soo Park, Kukhan Yoon, Joon Kim, Cheolhong Kim, Seokwoo Nam
  • Patent number: 8614148
    Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Soo Park, Jongchul Park, Cheolhong Kim, Seokwoo Nam, Kukhan Yoon
  • Publication number: 20130260559
    Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 3, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Soo PARK, Kukhan YOON, Joon KIM, Cheolhong KIM, Seokwoo NAM
  • Publication number: 20130260562
    Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.
    Type: Application
    Filed: January 3, 2013
    Publication date: October 3, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joon-Soo PARK, Jongchul PARK, Cheolhong KIM, Seokwoo NAM, Kukhan YOON
  • Patent number: 8278221
    Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
  • Patent number: 8062981
    Abstract: A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: November 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-young Lee, Sang-gyun Woo, Joon-soo Park
  • Publication number: 20110269294
    Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.
    Type: Application
    Filed: July 13, 2011
    Publication date: November 3, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee