Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Abstract: A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the first spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.

Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer.

Abstract: A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

Abstract: A multiple exposure system and a multiple exposure method using the same enhance the resolution of the image of the mask pattern transferred to a substrate. The system includes NA controllers that provide excellent resolution with respect to the directions of the short axis and long axis of the mask pattern. In one form of the method, a first exposure process is performed using a first NA controller that provides excellent resolution with respect to the direction of the short axis of the mask pattern and subsequently, a second exposure process is performed using a second NA controller that provides excellent resolution with respect to the direction of the long axis of the mask pattern. Alternatively, the first exposure process and the second or high order exposure process can be sequentially performed using the first and second NA controllers simultaneously.

Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Abstract: A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

Abstract: Multi-exposure lithography systems are provided for improved overlay accuracy. In one aspect, a method for multi-exposure lithography operates by determining overlay parameters corresponding to each of a plurality of sub-layouts, inputting the overlay parameters into an exposure system, exposing each sub-layout to photoresist on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout, and developing the exposed photoresist after exposing all of the sub-layouts.

Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Abstract: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

Abstract: Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.