Abstract: The display device includes a display panel and a pixel. A compensator configured to calculate a degradation rate of the pixel based on an input gray level of first image data, and compensates the first image data based on the degradation rate to generate second image data. A data driver configured to generate a data signal based on the second image data and configured to supply the data signal to the pixel. The pixel includes a first element group and a second element group connected in series to each other, the first element group includes at least one first light emitting element, and the second element group includes at least one second light emitting element. The compensator is to calculate the degradation rate by applying first information on the number of the first light emitting elements and second information on the number of the second light emitting elements.

Abstract: A semiconductor device including a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer; a first electrode provided on a first surface of the first semiconductor layer; a second electrode provided on a first surface of the second semiconductor layer, the active layer being provided between the first surface of the first semiconductor layer and a second surface of the second semiconductor layer that is opposite to the first surface of the second semiconductor layer; a first insulation layer provided on the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and a side surface of the active layer; a first cover electrode provided on the first electrode; a second cover electrode provided on the second electrode, a second insulation layer provided on the first cover electrode, the second cover electrode, and the first insulation layer, wherein: the second insulation layer includes a first opening over the

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: Provided are a negative electrode active material including a three-dimensional composite. The three-dimensional composite includes secondary particles containing a silicon carbide-based (SiCx, 0<x?1) nanosheet having a bent portion and amorphous carbon. Also provided are a method of producing the same, and a negative electrode and a lithium secondary battery including the negative electrode active material.

Abstract: A pressing jig for removing gas generated in an activation process of a battery cell includes a plate-shaped lower plate on which the battery cell that has undergone the activation process is placed and fixed, and an upper plate that presses the battery cell placed on the lower plate from above. At least one of the upper plate or the lower plate has a structure in which n (n?3) separated sub-plates are assembled to form a single plate, and the sub-plates independently press the battery cell. The pressing jig can suppress trapping of internal gas by sequentially pressing the battery cell.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.

Abstract: The present invention relates to use of miR-18b for prevention, treatment, or diagnosis of muscle diseases or neuromuscular diseases, and specifically it was confirmed that, in a muscle disease by gene mutations model, gene mutations reduce miR-18b expression, cause dysregulation of miR-18b signaling pathways, and thus induce calcium signaling, cell differentiation inhibition, and apoptosis. Therefore, miR-18b of the present invention may be used as a target factor for diagnosing and treating muscle diseases caused by gene mutations such as ALS and DMD.

Abstract: The present invention relates to a method for activating a secondary battery. The present invention comprises: a primary charging step of charging a secondary battery including a positive electrode, a negative electrode, a separator, and an electrolyte; a room temperature-aging step of storing, at a room temperature, the secondary battery that has undergone the primary charging step; and a high temperature-aging step of storing, at a high temperature, the secondary battery that has undergone the room temperature-aging step, wherein charging/discharging is performed by alternately applying + current and ? current to the secondary battery at the end of the primary charging step. The method for activating a secondary battery according to the present invention includes alternately applying + current and ? current to the secondary battery at the end of the primary charging step to stabilize an SEI film, thereby shortening a following-up aging time.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: The present invention is a method for manufacturing a secondary battery. An electrode assembly and an electrolyte are accommodated into a body of a battery case. The body of the battery case has an accommodation part and a gas pocket part, and a passage that extends from the accommodation part to the outside discharges an internal gas from the accommodation part through the gas pocket part. The battery case is seated in a seating step on a support block, which has an inclined part on a side surface thereof, to support the battery case. The body is pressed to discharge a gas accommodated in the accommodation part through the gas pocket part in the battery case. This method allows easy discharging of internal gas while reducing discharge of the electrolyte with the gas.

Abstract: A gene and cell therapy using a cell fusion technology is proposed. Cells overexpressing hemagglutinin neuraminidase (HN) and fusion (F) proteins have effects of enhancing cell fusion with other cells, restoring cell damage through the cell fusion with damaged cells, and transferring a normal gene. Therefore, when a vector including genes encoding the HN and F proteins of the present invention or a cell transformed with the vector is clinically applied to neurodegenerative diseases, muscular diseases, and the like, an effect of reducing the damage of damaged cells through cell fusion can be expected.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: The present disclosure provides a pump including a housing having a shaft hole, a membrane assembly disposed inside the housing, and a shaft assembly mounted on the housing. The shaft assembly includes a shaft inserted into the shaft hole, and a sealing member disposed on an end portion of the shaft and having a plurality of contact regions on an inner surface of the housing along a longitudinal direction of the shaft.

Abstract: An electrode includes a unit body stack part formed by stacking at least one basic unit having a four-layer structure in which a first electrode, a first separator, a second electrode and a second separator are sequentially stacked. Each surface of the first separator and the second separator is coated with a coating material having adhesiveness, and the basic unit adheres to an adjacent radial unit in the unit body stack part. The electrode assembly of allows a heating and pressing process to be performed prior to a primary formation process so that a separator of one basic unit and a first electrode of the other basic unit to be adhered and fixed by a coating material coated on the separator, and thus a bending phenomenon caused by a difference in electrode expansion rates in a charging/discharging process is prevented.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: An apparatus for inspecting defects of a secondary battery having a pair of pressing jigs which press an outer surface of an electrode or a pouch accommodating the electrode assembly in directions corresponding to each other and on which a plurality of protrusions protrude from pressing surfaces and a measurement unit measuring one or more of current, a voltage, and resistance of the electrode assembly when the electrode assembly is pressed by the plurality of protrusions of the pair of pressing jigs is provided.