Abstract: The present invention comprises: a pre-aging step for aging, at room temperature, a secondary battery comprising a cathode including a cathode active material, an anode including an anode active material, a separator interposed between the cathode and the anode, and an electrolyte (S100); a first charging step for primarily charging the pre-aged secondary battery to an SOC of the secondary battery of 60% or higher (S200); a high-temperature aging step for aging the primarily charged secondary battery at a high temperature (S300); and a room-temperature aging step for aging the high-temperature aged secondary battery at room temperature (S400), wherein the room-temperature aging step comprises a resetting process for charging the secondary battery to the same SOC as in the first charging step.

Abstract: A charging and discharging apparatus including a temperature measuring device suitable for measuring a temperature of each secondary battery and a cooling fan for cooling secondary batteries by utilizing temperature information using the temperature measuring device, such that a temperature deviation between the secondary batteries, which may occur during charging and discharging in a formation process and a capacity test after a secondary battery assembly process, is provided. The charging and discharging apparatus includes a movable non-contact temperature measuring device and cooling fans of which directions of wind and outputs are individually adjusted based on temperature information measured by the temperature measuring device according to a location in each secondary battery.

Abstract: An embodiment provides a semiconductor device including a light-emitting structure including a plurality of light-emitting portions disposed at a side and a plurality of second light-emitting portions disposed at another side, a plurality of first connection electrodes configured to electrically connect the plurality of first light-emitting portions, a plurality of second connection electrodes configured to electrically connect the plurality of second light-emitting portions, a first pad disposed on the plurality of first light-emitting portions, and a second pad disposed on the plurality of second light-emitting portions. The first pad includes a plurality of 1-2 pads extending toward the second pad. The second pad includes a plurality of 2-2 pads extending toward the first pad. The first connection electrode includes a region between the plurality of 1-2 pads in a thickness direction of the light-emitting structure.

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A formation jig includes a pressing plate configured to press a battery cell, the pressing plate having a first through hole; a pressing support plate configured to support the battery cell when the pressing plate presses an upper or lower portion of the battery cell, the pressing support plate having a second through hole and a third through hole; a first screw configured to pass through first through hole of the pressing plate and the second through hole of the pressing support plate and to move the pressing plate in a gap-adjusting direction by rotation thereof; and a second screw configured to pass through the third through hole of the pressing support plate and to move the pressing support plate in the gap-adjusting direction by rotation thereof. A diameter of the second through hole is larger than a diameter of the first through hole.

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: The present invention relates to use of miR-18b for prevention, treatment, or diagnosis of muscle diseases or neuromuscular diseases, and specifically it was confirmed that, in a muscle disease by gene mutations model, gene mutations reduce miR-18b expression, cause dysregulation of miR-18b signaling pathways, and thus induce calcium signaling, cell differentiation inhibition, and apoptosis. Therefore, miR-18b of the present invention may be used as a target factor for diagnosing and treating muscle diseases caused by gene mutations such as ALS and DMD.

Abstract: A lift pin module includes a lift pin which includes a head portion disposed at a first end of the lift pin, and a connecting portion disposed at a second end of the lift pin opposite to the first end, the head portion connected to a stage disposed inside a semiconductor process chamber, and the head portion extending in a first direction; an upper weight which includes a side surface with an opening extending in the first direction, the opening configured to receive the lift pin therein, and the upper weight surrounding the connecting portion of the lift pin; and a lower weight screwed to the upper weight, the lower weight disposed below the upper weight.

Abstract: A top cap for a secondary battery includes a circumferential area which defines an outer circumferential surface of the top cap, a central area which defines a central portion of the top cap, a connection area which connects the circumferential area to the central area, and a protrusion area which protrudes downward from the circumferential area, the central area, or the connection area. The top cap is assembled with a battery case, an electrode assembly positioned therein, and a through-hole formation member to form a secondary battery, in which at least a portion of the protrusion area of the top cap is positioned within a through-hole of the through-hole formation member.

Abstract: A degassing apparatus for a secondary battery, and a degassing method using same, is provided. The degassing apparatus includes a drive motor and a jig arm configured to pressurize a first surface of a gas pocket of a battery cell and a second surface opposite the first surface by controlling a separation distance by the operation of a driving motor. The degassing apparatus is capable of performing an effective degassing and sealing process for the battery cell without positional movement of the battery cell during cell activation or after cell activation.

Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region disp