Patents by Inventor Joon Sung AN
Joon Sung AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11850288Abstract: A gene and cell therapy using a cell fusion technology is proposed. Cells overexpressing hemagglutinin neuraminidase (HN) and fusion (F) proteins have effects of enhancing cell fusion with other cells, restoring cell damage through the cell fusion with damaged cells, and transferring a normal gene. Therefore, when a vector including genes encoding the HN and F proteins of the present invention or a cell transformed with the vector is clinically applied to neurodegenerative diseases, muscular diseases, and the like, an effect of reducing the damage of damaged cells through cell fusion can be expected.Type: GrantFiled: June 30, 2020Date of Patent: December 26, 2023Assignee: CURAMYS INC.Inventors: Jung-Joon Sung, Seung-Yong Seong, Hee-Woo Lee, Ki Yoon Kim
-
Publication number: 20230413545Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: ApplicationFiled: August 4, 2023Publication date: December 21, 2023Inventors: Sung Min Hwang, Joon Sung Lim, Bum Kyu Kang, Jae Ho Ahn
-
Patent number: 11844211Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.Type: GrantFiled: June 7, 2021Date of Patent: December 12, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ho Ahn, Ji Won Kim, Sung-Min Hwang, Joon-Sung Lim, Suk Kang Sung
-
Publication number: 20230381409Abstract: The present disclosure provides a pump including a housing having a shaft hole, a membrane assembly disposed inside the housing, and a shaft assembly mounted on the housing. The shaft assembly includes a shaft inserted into the shaft hole, and a sealing member disposed on an end portion of the shaft and having a plurality of contact regions on an inner surface of the housing along a longitudinal direction of the shaft.Type: ApplicationFiled: August 11, 2023Publication date: November 30, 2023Applicant: EOFLOW CO., LTD.Inventors: Do Kyung LEE, Joon Sung Jeon, Young Wook Chang
-
Patent number: 11824154Abstract: An electrode includes a unit body stack part formed by stacking at least one basic unit having a four-layer structure in which a first electrode, a first separator, a second electrode and a second separator are sequentially stacked. Each surface of the first separator and the second separator is coated with a coating material having adhesiveness, and the basic unit adheres to an adjacent radial unit in the unit body stack part. The electrode assembly of allows a heating and pressing process to be performed prior to a primary formation process so that a separator of one basic unit and a first electrode of the other basic unit to be adhered and fixed by a coating material coated on the separator, and thus a bending phenomenon caused by a difference in electrode expansion rates in a charging/discharging process is prevented.Type: GrantFiled: December 19, 2019Date of Patent: November 21, 2023Assignee: LG ENERGY SOLUTION, LTD.Inventors: Suk Hyun Hong, Eui Kyung Lee, Hyo Jin Park, Joon Sung Bae, Beom Koon Lee, Dong Hun Bae
-
Patent number: 11817387Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.Type: GrantFiled: May 23, 2022Date of Patent: November 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Gn Yun, Jaesun Yun, Joon-Sung Lim
-
Patent number: 11796595Abstract: An apparatus for inspecting defects of a secondary battery having a pair of pressing jigs which press an outer surface of an electrode or a pouch accommodating the electrode assembly in directions corresponding to each other and on which a plurality of protrusions protrude from pressing surfaces and a measurement unit measuring one or more of current, a voltage, and resistance of the electrode assembly when the electrode assembly is pressed by the plurality of protrusions of the pair of pressing jigs is provided.Type: GrantFiled: July 10, 2018Date of Patent: October 24, 2023Assignee: LG ENERGY SOLUTION, LTD.Inventors: Joon Sup Kang, Sung Tae Kim, Nak Gi Sung, Joon Sung Bae
-
Patent number: 11792982Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.Type: GrantFiled: September 21, 2020Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woosung Yang, Hojun Seong, Joonhee Lee, Joon-Sung Lim, Euntaek Jung
-
Patent number: 11778821Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.Type: GrantFiled: September 29, 2020Date of Patent: October 3, 2023Inventors: Joon Sung Kim, Byoung Il Lee, Seong-Hun Jeong, Jun Eon Jin
-
Publication number: 20230308191Abstract: Devices included in a wireless neural interface system are disclosed.Type: ApplicationFiled: November 15, 2022Publication date: September 28, 2023Inventors: Joon Sung BAE, Young Cheol CHAE, Byeong Seol KIM, Chang Uk LEE
-
Publication number: 20230293487Abstract: The present disclosure relates to a pharmaceutical composition for preventing or treating an inflammatory disease, comprising a benzofuran-based N-acylhydrazone compound, a stereoisomer thereof, or a pharmaceutically acceptable salt thereof. The benzofuran-based N-acylhydrazone compound according to the present disclosure inhibits the activity of NF-?B, which is a major signal transmitter in the inflammatory response, thereby disrupting the initial pathway and process of the biological inflammatory response system and inhibiting inflammatory immune cells and inflammatory cytokines, and thus can prevent and treat various pathological diseases caused by the inflammatory response.Type: ApplicationFiled: July 21, 2021Publication date: September 21, 2023Inventors: Joon Sung Hwang, Bo Yeon Kim, Nak Kyun Soung, Kyung Ho Lee, Seung Cheol Lee, Hyun Joo Cha
-
Patent number: 11758719Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: GrantFiled: August 2, 2021Date of Patent: September 12, 2023Inventors: Sung Min Hwang, Joon Sung Lim, Bum Kyu Kang, Jae Ho Ahn
-
Publication number: 20230282769Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region dispType: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Applicant: Photon Wave Co., Ltd.Inventors: Youn Joon SUNG, Seung Kyu OH, Jae Bong SO, Gil Jun LEE, Won Ho KIM, Tae Wan KWON, Eric OH, Il Gyun CHOI, Jin Young JUNG
-
Publication number: 20230266138Abstract: A charging station recommendation device and a method therefor include a data collection device that collects real-time information of at least one charging station and real-time information of at least one vehicle associated with the at least one charging station, a data processing device that generates charging information including a congestion of the at least one charging station, based on the real-time information of the at least one charging station and the real-time information of the at least one vehicle, a data storage storing the charging information of the at least one charging station, and a data application device that recommends an optimal charging station among the at least one charging station to a host vehicle, based on the charging information of the at least one charging station, which is stored in the data storage.Type: ApplicationFiled: October 6, 2022Publication date: August 24, 2023Applicants: Hyundai Motor Company, Kia CorporationInventors: Won Seok YANG, Joon Sung KWON
-
Patent number: 11728304Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.Type: GrantFiled: April 26, 2021Date of Patent: August 15, 2023Inventors: Jae Ho Ahn, Ji Won Kim, Sung-Min Hwang, Joon-Sung Lim, Suk Kang Sung
-
Patent number: 11728506Abstract: A device for charging and discharging a battery cell capable of suppressing a swelling phenomenon of a terrace portion of a battery cell during a formation process of the battery cell includes first and second plates configured to receive a battery cell therebetween and to press two surfaces of the battery cell; first and second grippers connected to the first and second plates, respectively, the first and second grippers protrude to face each other and configured to contact a lead region of the battery cell; and first and second pressing pads positioned inward of the first and second grippers, the first and second pressing pads being configured to contact a terrace region of the battery cell. A method of charging and discharging a battery cell using the same is also provided.Type: GrantFiled: November 22, 2021Date of Patent: August 15, 2023Assignee: LG ENERGY SOLUTION, LTD.Inventors: Suk Hyun Hong, Joon Sung Bae, Eui Kyung Lee, Sang Jih Kim, Beom Koon Lee, Dong Hun Bae
-
Patent number: 11715712Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.Type: GrantFiled: May 18, 2021Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Hwang, Ji Won Kim, Jae Ho Ahn, Joon-Sung Lim, Suk Kang Sung
-
Patent number: 11715713Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.Type: GrantFiled: August 18, 2021Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Won Kim, Jae Ho Ahn, Sung-Min Hwang, Joon-Sung Lim, Suk Kang Sung
-
Publication number: 20230238419Abstract: An embodiment discloses an ultraviolet light-emitting device including: a light-emitting structure including a plurality of light-emitting portions disposed on a first conductive type semiconductor layer, the plurality of light-emitting portions including an active layer and a second conductive type semiconductor layer; a first contact electrode disposed on the first conductive type semiconductor layer; a second contact electrode disposed on the second conductive type semiconductor layer; a first cover electrode disposed on the first contact electrode; and a second cover electrode disposed on the second contact electrode, wherein the light-emitting structure includes an intermediate layer formed in an etched region through which the first conductive type semiconductor layer is exposed, the intermediate layer including a lower composition of aluminum than the first conductive type semiconductor layer, wherein the intermediate layer includes a first intermediate region disposed between the plurality of light-emType: ApplicationFiled: September 24, 2021Publication date: July 27, 2023Applicant: Photon Wave Co., Ltd.Inventors: Youn Joon SUNG, Hae Jin PARK, Seung Kyu OH, Jae Bong SO, Gil Jun LEE, Il Gyun CHOI
-
Publication number: 20230224172Abstract: An integrated circuit is provided which includes a physically unclonable function (PUF). The integrated circuit comprises a PUF block including a plurality of physically unclonable function (PUF) cells configured to output a cell signal having a unique value according to an input, a conversion unit is configured to receive the cell signal as input, convert the cell signal, and output a conversion signal. A select signal generator provides a first selection signal to the conversion unit. A key generator is configured to receive the conversion signal from the conversion unit and generate a security key therefrom, wherein the conversion unit includes a first layer which outputs a second signal obtained by converting a provided first signal on the basis of a bit value of the first selection signal.Type: ApplicationFiled: September 26, 2022Publication date: July 13, 2023Applicant: Industry-Academic Cooperation Foundation, Yonsei UniversityInventor: Joon-Sung YANG