Patents by Inventor Joon-Sung Kim

Joon-Sung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10999544
    Abstract: An image sensor includes a pixel array that includes a first pixel group and a second pixel group, each including a plurality of image pixels to generate image data. The first pixel group includes a first phase detection pixel pair including first phase detection pixels arranged adjacent to each other in a first direction and having at least one first microlens thereon, and the second pixel group includes a second phase detection pixel pair including second phase detection pixels arranged adjacent to each other in a second direction different from the first direction and having at least one second microlens thereon. The sensitivity of the first phase detection pixels is different from the sensitivity of the second phase detection pixels.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 4, 2021
    Inventors: Tae-shick Wang, Chae-sung Kim, Sung-jin Park, Joon-hyuk Im
  • Patent number: 10966202
    Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-seok Jung, Min-goo Kim, In-hyoung Kim, Joon-sung Kim, Se-bin Im
  • Patent number: 10825934
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
  • Publication number: 20200144427
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: JOON-YOUNG KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE
  • Patent number: 10622273
    Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Young Choi, Joon Sung Kim, Young Min Kim, Da Hee Kim, Tae Wook Kim, Byung Ho Kim
  • Patent number: 10616898
    Abstract: A chipset is provided. The chipset is configured to detect an interference characteristic of a neighbor cell corresponding to groups and perform an interference whitening operation based on the interference characteristic. The groups are generated by dividing a time interval occupied by a first reference signal region by dividing a frequency band occupied by the first reference signal region, or by dividing a time interval occupied by a second reference signal region. A frequency band occupied by the second reference signal region is wider than the frequency band occupied by the first reference signal region.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Won Je, Dong-Sik Kim, Joon-Sung Kim, Young-Seok Jung
  • Publication number: 20200077401
    Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-seok Jung, Min-goo Kim, ln-hyoung Kim, Joon-sung Kim, Se-bin Im
  • Patent number: 10529865
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
  • Patent number: 10524264
    Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-seok Jung, Min-goo Kim, In-hyoung Kim, Joon-sung Kim, Se-bin Im
  • Patent number: 10402620
    Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Ho Kim, Da Hee Kim, Joon Sung Kim, Joo Young Choi, Hee Sook Park, Tae Wook Kim
  • Patent number: 10385166
    Abstract: The polyamide resin of the present invention is a polymer of a monomer mixture including a dicarboxylic acid and an amine-based compound, wherein the amine-based compound comprises diamine and triamine and a branching rate measured using 1H-NMR is approximately 1% to approximately 8%.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 20, 2019
    Assignee: Lotte Advanced Materials Co., Ltd.
    Inventors: So Young Kwon, Joon Sung Kim, Jin Kyu Kim, Sang Kyun Im, Il Kyoung Kwon, Ki Chul Son, Young Sub Jin, Sung Chul Choi
  • Publication number: 20190206755
    Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.
    Type: Application
    Filed: June 12, 2018
    Publication date: July 4, 2019
    Inventors: Joo Young CHOI, Joon Sung KIM, Young Min KIM, Da Hee KIM, Tae Wook KIM, Byung Ho KIM
  • Publication number: 20190206756
    Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, including a cavity penetrating through the first and second surfaces, and having a primer layer disposed on the first surface; a connection member disposed on the first surface of the support member and having a redistribution layer, the primer layer being disposed between the connection member and the support member; a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, the connection pads being electrically connected to the redistribution layer; and an encapsulant covering the second surface of the support member and the inactive surface of the semiconductor chip.
    Type: Application
    Filed: August 31, 2018
    Publication date: July 4, 2019
    Inventors: Joon Sung KIM, Doo Hwan LEE, Joo Young CHOI, Byung Ho KIM, Da Hee KIM, Tae Wook KIM
  • Publication number: 20190130152
    Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
    Type: Application
    Filed: May 16, 2018
    Publication date: May 2, 2019
    Inventors: Byung Ho KIM, Da Hee KIM, Joon Sung KIM, Joo Young CHOI, Hee Sook PARK, Tae Wook KIM
  • Publication number: 20190035942
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Application
    Filed: April 27, 2018
    Publication date: January 31, 2019
    Inventors: Joon-Young KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE
  • Patent number: 10134695
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan Lee, Ju Hyeon Kim, Hyoung Joon Kim, Joon Sung Kim
  • Publication number: 20180270824
    Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.
    Type: Application
    Filed: January 12, 2018
    Publication date: September 20, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-seok JUNG, Min-goo KIM, In-hyoung KIM, Joon-sung KIM, Se-bin IM
  • Publication number: 20180127545
    Abstract: A copolymerized polyamide resin includes a polymer of a monomer mixture comprising a dicarboxylic acid component comprising adipic acid and a dicarboxylic acid represented by Formula 1, wherein each R1 is independently a C1 to C5 alkyl group and a is an integer from 0 to 4, and a diamine component comprising m-xylene diamine and a diamine represented by Formula 2, wherein A is a single bond or a C1 to C10 hydrocarbon group, R2 and R3 are each independently a C1 to C5 alkyl group, and b and c are each independently an integer from 0 to 4, wherein the copolymerized polyamide resin has a difference between a melting temperature (Tm) and a crystallization temperature (Tc) of about 50° C. or more. The copolymerized polyamide resin may have excellent heat resistance and reduced or no gel generation and yellowing phenomenon in a molding process.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Inventors: So Young KWON, Jin Kyu KIM, Young Sub JIN, Joon Sung KIM, Ki Yon LEE, Suk Min JUN
  • Publication number: 20180082962
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.
    Type: Application
    Filed: March 15, 2017
    Publication date: March 22, 2018
    Inventors: Doo Hwan LEE, Ju Hyeon KIM, Hyoung Joon KIM, Joon Sung KIM
  • Publication number: 20180070365
    Abstract: A chipset is provided. The chipset is configured to detect an interference characteristic of a neighbor cell corresponding to groups and perform an interference whitening operation based on the interference characteristic. The groups are generated by dividing a time interval occupied by a first reference signal region by dividing a frequency band occupied by the first reference signal region, or by dividing a time interval occupied by a second reference signal region. A frequency band occupied by the second reference signal region is wider than the frequency band occupied by the first reference signal region.
    Type: Application
    Filed: July 7, 2017
    Publication date: March 8, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hui-Won JE, Dong-Sik KIM, Joon-Sung KIM, Young-Seok JUNG