Patents by Inventor Joon-soo Park
Joon-soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250066275Abstract: The present invention relates to an anthracene derivative compound having a characteristic structure in which an aryl group is introduced into a skeletal structure in which deuterium-substituted phenyl and anthracene are linked. In addition, the present invention relates to a high-efficiency, long-life organic light-emitting device of which the luminous efficiency and lifetime characteristics are significantly improved by employing a polycyclic compound having a characteristic structure as a dopant for a light-emitting layer while employing said compound as a host for the light-emitting layer.Type: ApplicationFiled: December 14, 2022Publication date: February 27, 2025Applicant: SFC CO., LTD.Inventors: Se-jin LEE, Si-In KIM, Seok-bae PARK, Hee-dae KIM, Yeong-tae CHOI, Kyung-tae KIM, Ji-yung KIM, Seung-soo LEE, Kyeong-hyeon KIM, Tae-gyun LEE, Joon-ho KIM
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Publication number: 20250063948Abstract: The present invention relates to an organic light-emitting diode in which a light-emitting layer comprises a compound represented by [chemical formula A] as a host and comprises a compound represented by [chemical formula 3], [chemical formula 4], [chemical formula 3-1] to [chemical formula 4-3] as a dopant, wherein [chemical formula 3], [chemical formula 4], [chemical formula 3-1] to [chemical formula 4-3] are the same as those described in the detailed description of the invention.Type: ApplicationFiled: November 25, 2022Publication date: February 20, 2025Inventors: Kyung-Tae KIM, Se-Jin LEE, Si-In KIM, Seok-Bae PARK, Hee-Dae KIM, Yeong-Tae CHOI, Ji-Yung KIM, Seung-Soo LEE, Kyeong-Hyeon KIM, Tae-Gyun LEE, Joon-Ho KIM
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Publication number: 20250056970Abstract: A display device includes a pixel electrode in a light emission area, a pixel defining layer which is on the pixel electrode and defines the light emission area, a light emitting layer and a common electrode on the pixel electrode, a bank on the pixel defining layer, the bank including a first bank layer defining a lower portion of a bank opening corresponding to the light emission area and a second bank layer which defines an upper portion of the bank opening and a tip of the bank, the tip including upper and lower surfaces of the second bank layer, a lower inorganic encapsulation layer which is on the bank and includes an inorganic pattern on the common electrode and facing and spaced apart from both the upper and lower surfaces of the tip, and an auxiliary pattern between the lower surface of the tip and the inorganic pattern.Type: ApplicationFiled: March 8, 2024Publication date: February 13, 2025Inventors: Hyun Eok SHIN, Su Kyoung YANG, Dong Min LEE, Joon Yong PARK, Byung Soo SO, Yung Bin CHUNG
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Publication number: 20250056932Abstract: Disclosed are a display device and a method of manufacturing the display device. The display device includes a display panel on which a plurality of sub-pixels and lines connected to the sub-pixels and a driving circuit configured to drive the sub-pixels. The display panel further includes a plurality of protruded bank patterns disposed in the sub-pixels, and a light emitting element disposed in each of the bank patterns. The light emitting element includes a first electrode, a second electrode, a light emitting layer disposed between the first electrode and the second electrode, and a reflector that covers side surfaces of the light emitting layer and at least a portion of side surfaces of the first electrode. The reflector includes a first insulating layer, a second insulating layer, and a metal layer disposed between the first insulating layer and the second insulating layer.Type: ApplicationFiled: August 8, 2024Publication date: February 13, 2025Inventors: Hyun Chyol Shin, Seong Soo Cho, Hee Won Lee, Han Saem Kang, Sang Hak Shin, Hyoung Sun Park, Hyun Seok Na, Jin Hwa Shin, Joon Kwon Moon
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Publication number: 20250031162Abstract: A method according to an embodiment of the present invention corresponds to a method for transmitting, by a gateway, a synchronization signal block (SSB) through a plurality of satellites, and may comprise the steps of: determining satellite identification SSBs for identifying a plurality of satellites, respectively; determining beam identification SSBs for identifying beams usable for the plurality of satellites, respectively; and controlling the satellite identification SSBs and the beam identification SSBs to be transmitted to the plurality of satellites, respectively, through a predetermined resource, wherein the satellite identification SSBs and each of the beam identification SSBs have different SSB indices from each other.Type: ApplicationFiled: November 23, 2022Publication date: January 23, 2025Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Gyeong Rae IM, Jung Bin KIM, Pan Soo KIM, Min Su SHIN, In Ki LEE, Dong Hyun JUNG, Soo Yeob JUNG, Seung Keun PARK, Joon Gyu RYU
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Patent number: 12201045Abstract: Disclosed herein is a frame apparatus for an agricultural work vehicle. The frame apparatus includes: an engine frame configured to support the engine of an agricultural work vehicle; a front frame connected to each of a front work machine and the engine frame to support the front work machine mounted in front of the agricultural work vehicle; a center case spaced apart from the front frame based on a first axis direction, and disposed behind the engine frame; a rear axle case coupled to the rear of the center case; side frames each coupled to each of the front frame and the rear axle case on both sides of the agricultural work vehicle; and a crossbar coupled to the side frames while connecting the side frames on both sides based on a second axis direction perpendicular to the first axis direction.Type: GrantFiled: October 10, 2023Date of Patent: January 21, 2025Assignee: LS MTRON LTD.Inventors: Ji Soo Park, Hyo Jong Chon, Han Yeol Yu, Joon Hyung Kim
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Patent number: 12205323Abstract: Disclosed herein are an apparatus for estimating a camera pose using multi-view images of a 2D array structure and a method using the same. The method performed by the apparatus includes acquiring multi-view images from a 2D array camera system, forming a 2D image link structure corresponding to the multi-view images in consideration of the geometric structure of the camera system, estimating an initial camera pose based on an adjacent image extracted from the 2D image link structure and a pair of corresponding feature points, and estimating a final camera pose by reconstructing a 3D structure based on the initial camera pose and performing correction so as to minimize a reprojection error of the reconstructed 3D structure.Type: GrantFiled: March 23, 2022Date of Patent: January 21, 2025Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, SOGANG UNIVERSITY RESEARCH FOUNDATIONInventors: Joon-Soo Kim, Kug-Jin Yun, Jun-Young Jeong, Suk-Ju Kang, Jung-Hee Kim, Woo-June Park
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Publication number: 20250023682Abstract: The present invention relates to a method for transmitting a synchronization signal block (SSB) through a plurality of satellites from a base station that can connect to a plurality of gateways, wherein the method may comprise the steps of: controlling transmission of first SSBs corresponding to the number of beams of each satellite through respective transmission beams in a first SSB cycle; determining a transmission beam of each of the satellites on the basis of a first measurement report for the respective beams received from a terminal; and controlling transmission of second SSBs for determining one combination including two or more gateways among the plurality of gateways in a second SSB cycle.Type: ApplicationFiled: November 23, 2022Publication date: January 16, 2025Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Gyeong Rae IM, Jung Bin KIM, Pan Soo KIM, Min Su SHIN, In Ki LEE, Dong Hyun JUNG, Soo Yeob JUNG, Seung Keun PARK, Joon Gyu RYU
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Patent number: 11473079Abstract: The present invention relates to a method for prenatal diagnosis using digital PCR, and more particularly to a method for providing information for diagnosis of chromosomal aneuploidy in a fetus, comprising: (a) extracting DNAs from pregnant woman's blood; (b) classifying the DNAs according to size to obtain DNAs having a size of 1,000 bp or less; (c) performing digital PCR using the obtained DNAs of step (b), for a control gene located on a chromosome not associated with chromosomal aneuploidy and a target gene located on a chromosome associated with chromosomal aneuploidy; (d) calculating a ratio of a quantitative digital PCR value of the target gene to a quantitative digital PCR value of the control gene; and (e) determining that when the ratio calculated in step (d) is 0.70-1.14, a chromosome number of the fetus is normal.Type: GrantFiled: October 28, 2016Date of Patent: October 18, 2022Assignee: BIOCORE CO., LTD.Inventors: Seung Yong Hwang, Moon Ju Oh, Seung Jun Kim, Jong Pil Youn, Ji Hoon Kim, Seung Yong Lee, Jeong Jin Ahn, Joon Soo Park, Hyo Jung Choi
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Publication number: 20220118308Abstract: According to the present disclosure, provided is a hip-up exercise apparatus. The hip-up exercise apparatus includes a frame defining an opening at one side thereof and fixing holes at both sides of upper surfaces thereof; a footrest portion disposed at the opening of the frame; a pair of pillars inserted into and coupled to the fixing holes of the frame; and a back supporter connecting upper portions of the pair of pillars and configured to support a back; and the pillars are separated from the fixing holes, are rotated downward, and are turned over, to attach rear surfaces of the pillars to upper surfaces of the frame.Type: ApplicationFiled: October 23, 2020Publication date: April 21, 2022Inventor: Joon-soo Park
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Patent number: 10553438Abstract: A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate.Type: GrantFiled: January 19, 2017Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun Kyeong Jang, Sang Jin Kim, Dong Woon Park, Joon Soo Park, Chang Jae Yang, Kwang Sub Yoon, Hye Kyoung Jue
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Patent number: 10276373Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.Type: GrantFiled: April 19, 2017Date of Patent: April 30, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Chul Jeong, Tae Kyu Lee, Sung Sik Park, Joon Soo Park, Kwang Sub Yoon, Boo Hyun Ham
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Publication number: 20190100749Abstract: The present invention relates to a method for prenatal diagnosis using digital PCR, and more particularly to a method for providing information for diagnosis of chromosomal aneuploidy in a fetus, comprising: (a) extracting DNAs from pregnant woman's blood; (b) classifying the DNAs according to size to obtain DNAs having a size of 1,000 bp or less; (c) performing digital PCR using the obtained DNAs of step (b), for a control gene located on a chromosome not associated with chromosomal aneuploidy and a target gene located on a chromosome associated with chromosomal aneuploidy; (d) calculating a ratio of a quantitative digital PCR value of the target gene to a quantitative digital PCR value of the control gene; and (e) determining that when the ratio calculated in step (d) is 0.70-1.14, a chromosome number of the fetus is normal.Type: ApplicationFiled: October 28, 2016Publication date: April 4, 2019Inventors: Seung Yong Hwang, Moon Ju Oh, Seung Jun Kim, Jong Pil Youn, Ji Hoon Kim, Seung Yong Lee, Jeong Jin Ahn, Joon Soo Park, Hyo Jung Choi
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Publication number: 20180096840Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.Type: ApplicationFiled: April 19, 2017Publication date: April 5, 2018Inventors: Yong Chul JEONG, Tae Kyu LEE, Sung Sik PARK, Joon Soo PARK, Kwang Sub YOON, Boo Hyun HAM
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Publication number: 20170372906Abstract: A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate.Type: ApplicationFiled: January 19, 2017Publication date: December 28, 2017Inventors: Yun Kyeong JANG, Sang Jin KIM, Dong Woon PARK, Joon Soo PARK, Chang Jae YANG, Kwang Sub YOON, Hye Kyoung JUE
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Publication number: 20150309411Abstract: Methods of forming a pattern are provided. The methods may include forming a dual tone photoresist layer on a support layer, forming a low light exposure region, a middle light exposure region, and a high light exposure region in a first region of the dual tone photoresist layer and forming a low light exposure region and a middle light exposure region in a second region of the dual tone photoresist layer by exposing the dual tone photoresist layer to light by using a mask comprising a gray feature. The method may also include forming preliminary patterns in the first region by performing a positive development process and forming first patterns which are spaced apart from one another in the first region and second patterns which are spaced apart from one another in the second region by performing a negative development process.Type: ApplicationFiled: April 6, 2015Publication date: October 29, 2015Inventors: Sung-wook HWANG, Soon-mok HA, Joon-soo PARK
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Patent number: 8785319Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.Type: GrantFiled: March 13, 2013Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Soo Park, Kukhan Yoon, Joon Kim, Cheolhong Kim, Seokwoo Nam
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Patent number: 8614148Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.Type: GrantFiled: January 3, 2013Date of Patent: December 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Soo Park, Jongchul Park, Cheolhong Kim, Seokwoo Nam, Kukhan Yoon
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Publication number: 20130260562Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.Type: ApplicationFiled: January 3, 2013Publication date: October 3, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Joon-Soo PARK, Jongchul PARK, Cheolhong KIM, Seokwoo NAM, Kukhan YOON
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Publication number: 20130260559Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.Type: ApplicationFiled: March 13, 2013Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Soo PARK, Kukhan YOON, Joon KIM, Cheolhong KIM, Seokwoo NAM