Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: Disclosed herein is a percutaneous catheter apparatus, comprising two nested needles; and an inner plunger; which is guided as a catheter to the tissue surrounding a hard implant to actuate and deploy a pair of sharp-tip needle-forceps that perform two concentric cuts, circularly spaced 90-degree apart from each other, to complete a 360 degree bore around the implant before squeezing to arrest and extract the implant, together with its surrounding tissue.

Abstract: A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.

Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.

Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.

Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.

Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Abstract: A chipset is provided. The chipset is configured to detect an interference characteristic of a neighbor cell corresponding to groups and perform an interference whitening operation based on the interference characteristic. The groups are generated by dividing a time interval occupied by a first reference signal region by dividing a frequency band occupied by the first reference signal region, or by dividing a time interval occupied by a second reference signal region. A frequency band occupied by the second reference signal region is wider than the frequency band occupied by the first reference signal region.

Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.

Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.

Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

Abstract: The polyamide resin of the present invention is a polymer of a monomer mixture including a dicarboxylic acid and an amine-based compound, wherein the amine-based compound comprises diamine and triamine and a branching rate measured using 1H-NMR is approximately 1% to approximately 8%.

Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, including a cavity penetrating through the first and second surfaces, and having a primer layer disposed on the first surface; a connection member disposed on the first surface of the support member and having a redistribution layer, the primer layer being disposed between the connection member and the support member; a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, the connection pads being electrically connected to the redistribution layer; and an encapsulant covering the second surface of the support member and the inactive surface of the semiconductor chip.

Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.