Patents by Inventor Joon-Sung Kim
Joon-Sung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230210506Abstract: Disclosed herein is a percutaneous catheter apparatus, comprising two nested needles; and an inner plunger; which is guided as a catheter to the tissue surrounding a hard implant to actuate and deploy a pair of sharp-tip needle-forceps that perform two concentric cuts, circularly spaced 90-degree apart from each other, to complete a 360 degree bore around the implant before squeezing to arrest and extract the implant, together with its surrounding tissue.Type: ApplicationFiled: April 1, 2021Publication date: July 6, 2023Inventors: Fotios Papadimitrakopoulos, Allen Legassey, Joon-Sung Kim, Jun Kondo, Faquir Jain
-
Patent number: 10966202Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.Type: GrantFiled: November 8, 2019Date of Patent: March 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-seok Jung, Min-goo Kim, In-hyoung Kim, Joon-sung Kim, Se-bin Im
-
Patent number: 10825934Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: GrantFiled: January 6, 2020Date of Patent: November 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
-
Publication number: 20200144427Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: JOON-YOUNG KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE
-
Patent number: 10616898Abstract: A chipset is provided. The chipset is configured to detect an interference characteristic of a neighbor cell corresponding to groups and perform an interference whitening operation based on the interference characteristic. The groups are generated by dividing a time interval occupied by a first reference signal region by dividing a frequency band occupied by the first reference signal region, or by dividing a time interval occupied by a second reference signal region. A frequency band occupied by the second reference signal region is wider than the frequency band occupied by the first reference signal region.Type: GrantFiled: July 7, 2017Date of Patent: April 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hui-Won Je, Dong-Sik Kim, Joon-Sung Kim, Young-Seok Jung
-
Publication number: 20200077401Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Young-seok Jung, Min-goo Kim, ln-hyoung Kim, Joon-sung Kim, Se-bin Im
-
Patent number: 10529865Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: GrantFiled: April 27, 2018Date of Patent: January 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
-
Patent number: 10524264Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.Type: GrantFiled: January 12, 2018Date of Patent: December 31, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Young-seok Jung, Min-goo Kim, In-hyoung Kim, Joon-sung Kim, Se-bin Im
-
Publication number: 20190035942Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: ApplicationFiled: April 27, 2018Publication date: January 31, 2019Inventors: Joon-Young KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE
-
Publication number: 20180270824Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.Type: ApplicationFiled: January 12, 2018Publication date: September 20, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Young-seok JUNG, Min-goo KIM, In-hyoung KIM, Joon-sung KIM, Se-bin IM
-
Publication number: 20180070365Abstract: A chipset is provided. The chipset is configured to detect an interference characteristic of a neighbor cell corresponding to groups and perform an interference whitening operation based on the interference characteristic. The groups are generated by dividing a time interval occupied by a first reference signal region by dividing a frequency band occupied by the first reference signal region, or by dividing a time interval occupied by a second reference signal region. A frequency band occupied by the second reference signal region is wider than the frequency band occupied by the first reference signal region.Type: ApplicationFiled: July 7, 2017Publication date: March 8, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Hui-Won JE, Dong-Sik KIM, Joon-Sung KIM, Young-Seok JUNG
-
Patent number: 8710943Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment, an electromagnetic bandgap structure is stacked with a first metal layer, a first dielectric layer, a metal plate, a second dielectric layer and a second metal layer, and an odd number of vias can be serially connected through a metal line between the first metal layer and the metal plate. This electromagnetic bandgap structure can have a small size and a low bandgap frequency.Type: GrantFiled: January 31, 2013Date of Patent: April 29, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Kim, Hyung-Sik Choi, Sang-Hoon Kim, Joon-Sung Kim
-
Patent number: 8457450Abstract: A printed circuit board is disclosed. A printed circuit board, which includes a first board part, a flexible board part which has one side coupled with the first board part and which includes an electrical wiring layer and an optical waveguide to transmit both electrical signals and optical signals, and a second board part coupled with the other side of the flexible board part, where the electrical wiring layer and the optical waveguide are disposed with a gap in-between, can provide greater bendability and reliability, by having the optical waveguide and electrical wiring layer separated with a gap in-between at the flexible portion of the board, and the optical waveguide can be manufactured with greater precision for even higher reliability, by having the optical waveguide manufactured separately and then inserted during the manufacturing process of the board.Type: GrantFiled: December 10, 2008Date of Patent: June 4, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang-Hoon Kim, Je-Gwang Yoo, Joon-Sung Kim, Han Seo Cho
-
Patent number: 8426299Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.Type: GrantFiled: December 27, 2011Date of Patent: April 23, 2013Assignee: Samsung Electronics Co., LtdInventors: Joon-Sung Kim, Hye-Soo Shin, Mi-Youn Kim, Young-Soo Kim
-
Patent number: 8368488Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, an electromagnetic bandgap structure is stacked with a first metal layer, a first dielectric layer, a metal plate, a second dielectric layer and a second metal layer, and an odd number of vias can be serially connected through a metal line between the first metal layer and the metal plate. This electromagnetic bandgap structure can have a small size and a low bandgap frequency.Type: GrantFiled: June 11, 2008Date of Patent: February 5, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Kim, Hyung-Sik Choi, Sang-Hoon Kim, Joon-Sung Kim
-
Patent number: 8280204Abstract: An optical wiring board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the method includes providing a base substrate having an optical waveguide layer with a mirror groove formed on one surface thereof and a first insulation layer stacked on one surface of the optical waveguide layer and having a through-hole connected with the mirror groove formed thereon, forming a metal mirror layer connected from the mirror groove to an inner wall of the through-hole and forming an electrode pad on a side of the other surface of the optical waveguide layer, in which the electrode pad is disposed in accordance with the position of the metal mirror layer.Type: GrantFiled: April 14, 2010Date of Patent: October 2, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang-Hoon Kim, Han-Seo Cho, Joon-Sung Kim, Jae-Hyun Jung
-
Patent number: 8249403Abstract: An optical wiring board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the method includes providing a flexible optical waveguide layer, selectively forming a reinforcing clad on one surface of the optical waveguide layer and forming a mirror groove on the other surface of the optical waveguide layer in accordance with where the reinforcing clad is formed. Thus, the clad can be formed thick only on the place where the mirror groove is to be formed, and thus a flexible optical wiring board having flexibility can be manufactured even though the optical wiring board is generally made thin.Type: GrantFiled: April 16, 2010Date of Patent: August 21, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang-Hoon Kim, Han-Seo Cho, Joon-Sung Kim, Jae-Hyun Jung
-
Publication number: 20120199388Abstract: A printed circuit board including: an insulation layer; a first circuit pattern formed over one surface of the insulation layer, the first circuit pattern having a side thereof slanted with respect to the insulation layer; and a second circuit pattern formed over the other surface of the insulation layer, the second circuit pattern having a side thereof slanted with respect to the insulation layer, wherein the side of the second circuit pattern is less slanted than the side of the first circuit pattern.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Joon-Sung KIM, Je-Gwang YOO, Chang-Sup RYU
-
Publication number: 20120164821Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.Type: ApplicationFiled: December 27, 2011Publication date: June 28, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Joon-Sung KIM, Hye-Soo SHIN, Mi-Youn KIM, Young-Soo KIM
-
Patent number: 8201030Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.Type: GrantFiled: October 30, 2008Date of Patent: June 12, 2012Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seul-Ki Bae, Seung-Hee Han, Jong-Hyeuk Lee, Hong-Yeop Song, Dae-Son Kim, Joon-Sung Kim