Patents by Inventor Jordan D. Greenlee
Jordan D. Greenlee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10748921Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.Type: GrantFiled: October 25, 2018Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
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Patent number: 10727250Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: GrantFiled: June 4, 2019Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Publication number: 20200211843Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: David Ross Economy, Brian Beatty, John Mark Meldrim, Yongjun Jeff Hu, Jordan D. Greenlee
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Publication number: 20200161332Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.Type: ApplicationFiled: January 23, 2020Publication date: May 21, 2020Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
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Publication number: 20200152651Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: ApplicationFiled: January 7, 2020Publication date: May 14, 2020Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
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Publication number: 20200135751Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Applicant: Micron Technology, Inc.Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
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Publication number: 20200075620Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.Type: ApplicationFiled: August 16, 2019Publication date: March 5, 2020Applicant: Micron Technology, Inc.Inventors: Nancy M. Lomeli, Tom George, Jordan D. Greenlee, Scott M. Pook, John Mark Meldrim
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Patent number: 10573661Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.Type: GrantFiled: March 25, 2019Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
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Patent number: 10559579Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: GrantFiled: June 17, 2019Date of Patent: February 11, 2020Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
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Publication number: 20190333933Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: ApplicationFiled: June 4, 2019Publication date: October 31, 2019Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Publication number: 20190333924Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: ApplicationFiled: June 17, 2019Publication date: October 31, 2019Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
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Patent number: 10424596Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.Type: GrantFiled: December 22, 2017Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventors: Nancy M. Lomeli, Tom George, Jordan D. Greenlee, Scott M. Pook, John Mark Meldrim
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Patent number: 10361216Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: GrantFiled: September 20, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Patent number: 10361214Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: GrantFiled: November 9, 2018Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
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Publication number: 20190221580Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
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Publication number: 20190198518Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Nancy M. Lomeli, Tom George, Jordan D. Greenlee, Scott M. Pook, John Mark Meldrim
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Publication number: 20190189630Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: ApplicationFiled: November 9, 2018Publication date: June 20, 2019Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
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Patent number: 10283524Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.Type: GrantFiled: December 20, 2017Date of Patent: May 7, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
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Publication number: 20190088671Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: ApplicationFiled: September 20, 2017Publication date: March 21, 2019Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Patent number: 10170493Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: GrantFiled: December 20, 2017Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer