Abstract: Compressing memory addresses within an execution trace via reference to a translation lookaside buffer (TLB) entry. A microprocessor identifies a TLB entry within a TLB slot, the TLB entry mapping a virtual memory page to a physical memory page. The microprocessor initiates logging of the TLB entry by initiating logging of at least a virtual address of the virtual memory page, and an identifier that uniquely identifies the TLB entry from among a plurality of live TLB entries. Subsequently, the microprocessor identifies a cache entry within a memory cache slot, the cache entry comprising a physical memory address corresponding to a cache line. The microprocessor initiates logging of the cache entry by matching a physical memory page identification portion of the physical memory address with the TLB entry, and then initiates logging of at least the identifier for the TLB entry and an offset portion.

Abstract: Reducing overheads of recording a replayable execution trace of a program's execution at a computer processor by omitting logging of accesses to memory addresses whose values can be reconstructed or predicted. A computer system determines that memory values corresponding to a range of memory addresses within a memory space for a process can be obtained separately from the process' execution, and configures a data structure for instructing a processor to omit logging of memory accesses when the processor accesses an address within this range while executing the process. Correspondingly, upon detecting a memory access while executing the process, the processor determines if it has been instructed to omit logging of the access by checking the data structure. When the data structure instructs the processor to omit logging of the access, the processor omits logging the memory access while it uses a cache to process the memory access.

Abstract: Compressing memory addresses within an execution trace via reference to a translation lookaside buffer (TLB) entry. A microprocessor identifies a TLB entry within a TLB slot, the TLB entry mapping a virtual memory page to a physical memory page. The microprocessor initiates logging of the TLB entry by initiating logging of at least a virtual address of the virtual memory page, and an identifier that uniquely identifies the TLB entry from among a plurality of live TLB entries. Subsequently, the microprocessor identifies a cache entry within a memory cache slot, the cache entry comprising a physical memory address corresponding to a cache line. The microprocessor initiates logging of the cache entry by matching a physical memory page identification portion of the physical memory address with the TLB entry, and then initiates logging of at least the identifier for the TLB entry and an offset portion.

Abstract: Logging cache line lifetime hints when recording an execution trace. A microprocessor detects occurrence of a first cache event that initiates a lifetime of a cache line within a memory cache, and initiates logging first trace information indicating a beginning of the lifetime of the cache line within the memory cache. Subsequently, the microprocessor detects occurrence of a second cache event that ends the lifetime of the cache line within the memory cache. Based on detecting the second cache event, the microprocessor initiates logging second trace information indicating an ending of the lifetime of the cache line within the memory cache.

Abstract: Omitting or obfuscating physical memory addresses within an execution trace. A microprocessor identifies a first translation lookaside buffer (TLB) entry mapping a first virtual memory page to a physical memory page, and initiates logging of the first TLB entry by initiating logging of at least a first virtual address of the first virtual memory page and a first identifier. The microprocessor identifies a second TLB entry mapping a second virtual memory page to the physical memory page, and initiates logging of the second TLB entry by initiating logging of at least a second virtual address of the second virtual memory page and a second identifier. The microprocessor determines that the first and second TLB entries are each live, logged into the execution trace, and mapped to the same physical address, and ensures that the execution trace indicates that the first and second TLB entries each map to the physical address.

Abstract: Embodiments relate to a virtualization layer capturing replayable execution traces of VMs managed by the virtualization layer. Execution tracing can be performed on any unit of execution managed by the virtualization layer, e.g., threads, processes, virtual processors, individual VMs, multiple VMs, etc. Traced execution units may be executing in parallel. Execution tracing involves capturing to a buffer: executed instructions, memory inputted to instructions, memory outputted by instructions, registers touched by instructions, and ordering markers. Trace data can be captured in chunks, where causality is preserved and ordering is preserved between chunks but not necessarily within chunks. The chunks may be delineated by inserting monotonically increasing markers between context switches, thus relatively ordering the chunks. Determinism may be partially provided by identifying non-deterministic events. VM tracing may be transparent to guest software, which need not be instrumented.

Abstract: Trace recording based on data influxes to an outer-level cache and cache coherence protocol (CCP) transitions between inner caches. Example computing device(s) include a plurality of processing units, a plurality of (N-1)-level caches, and an N-level cache that is associated with two or more of the (N-1)-level caches and that is a backing store for the two or more (N-1)-level caches. Based at least on detecting influx(es) of data to a location in the N-level cache during execution across the processing units, the computing device(s) causes the influx(es) of data to be logged. The computing device(s) also causes one or more (N-1)-level CCP transitions between the two or more (N-1)-level caches to be logged. The (N-1)-level CCP transitions result from the location being accessed by two or more of the processing units.

Abstract: A tracing coprocessor that records execution trace data based on a cache coherency protocol (CCP) message. The tracing coprocessor comprises logic that causes the tracing coprocessor to listen on a bus that is communicatively coupled to a primary processor that executes executable code instructions. The logic also causes the tracing coprocessor to, based on listening on the bus, identify at least one CCP message relating to activity at a processor cache. The logic also causes the tracing coprocessor to identify, from the at least one CCP message, a memory cell consumption by the primary processor. The logic also causes the tracing coprocessor to initiate logging, into an execution trace, at least a memory cell data value consumed by the primary processor in connection with execution of at least one executable code instruction.

Abstract: During an execution of a first executable entity, a computer system determines that a target chunk of executable instructions is to be recorded during the execution. Prior to executing the target chunk of executable instructions, the computer system identifies one or more input(s) of the target chunk of executable instructions, and adjusts a page table entry to cause a page fault based on an access by a second executable entity to a first memory page that corresponds to an identified input, and/or an access by the first executable entity to a second memory page that does not correspond to any identified input. Based on detecting an occurrence of a page fault during an execution of the target chunk of executable instructions, the computer system detects that there an interference with an identified input by the second executable entity and/or an incompleteness of the identified inputs.

Abstract: A computer system that records a replayable execution trace based on recording cache coherency protocol (CCP) messages into a first trace, and on recording memory snapshot(s) into a second trace. Based on determining that tracing of execution of a first execution context is to be enabled, the computer system initiates logging, into the second trace, of one or more memory snapshots of a memory space of the first execution context, and enables a hardware tracing feature of a processor. Enabling the tracing feature causes the processor to log, into the first trace, CCP message(s) generated in response to one or more memory access into the memory space of the first execution context. After enabling the hardware tracing feature of the processor, the computer system also logs or otherwise handles a write into the memory space of the first execution context by a second execution context.

Abstract: Cache-based tracing based on categorizing memory regions as being logged or not logged. A computer system identifies a first memory region within a first memory space of a first context, and determines that the first context is in a logging state. The computer system configures a data structure to categorize the first memory region as being logged. The data structure also categorizes a second memory region corresponding to a second context as being not logged. The computer system exposes the data structure to a processor. Upon detecting a memory access by a processing unit, the processor uses determinations of one or more of (i) whether a target memory address is categorized as being logged or not logged, (ii) whether an executing context is logging or not non-logging, or (iii) a type of the memory access to initiate a logging action or refrain from the logging action.

Abstract: Mapping input locations to enable execution of second executable code using trace data gathered during execution of first executable code. A trace of a prior execution of the first code, and the second code, are accessed. The trace stores data of an input that was consumed by first executable instructions of the first code. It is determined that the stored data of the input is usable as an input to second executable instructions of the second code. A difference in how the first instructions accessed the input during recording, as compared to how the second instructions expect to access input, is identified. Based on the identified difference, a location transformation is determined that would enable the second instructions to access the stored data. Execution of the second instructions is emulated using the stored data, including projecting the location transformation to enable the second instructions to access the stored data.

Abstract: Automatic identification of execution behavior(s) of software. This automatic identification is based on analysis of historical execution records using machine learning to identify a particular pattern that corresponds to an execution behavior. In order to automatically identify an execution behavior present within particular software, an execution record of that particular software is accessed. The execution record includes an execution trace that reproducibly represents the execution of the software within a particular execution environment, such that the execution record is usable to rerun the execution of the software precisely as the software previously run. Based on finding the particular pattern within the execution record, the computing system automatically identifies that the execution behavior is present within the software.

Abstract: Diffing a subject replayable trace against a comparison replayable trace includes identifying a first plurality of functions within a first sequence of instructions recorded in the subject trace, and identifying a second plurality of functions a second sequence of instructions recorded in the comparison trace. A first plurality of groups of the first plurality of functions, and a second plurality of groups of the second plurality of functions are identified. The first and second pluralities of groups are compared, including determining, based on an identity of each group, and on function(s) corresponding to the group, if each first group in the first plurality of groups is at least one of: equal to a second group in the second plurality of groups, a replacement of a second group in the second plurality of groups, deleted from the second plurality of groups, or inserted into the second plurality of groups.

Abstract: Diffing a subject replayable trace against a plurality of comparison replayable traces includes identifying a set of mappings among the comparison replayable traces, each identifying corresponding comparison sections of consecutive instructions recorded in the comparison replayable traces that execute equivalently. A plurality of distinct comparison sections are identified within the comparison replayable traces. Each of a plurality of subject sections within the subject trace is compared against distinct comparison section(s) to determine a comparison status for each subject section, including whether each subject section is (i) equal to at least one corresponding distinct comparison section, or (ii) different than the distinct comparison sections.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: A processor that performs cache-based tracing based on recording one or more cache coherency protocol (CCP) messages into a first trace. Based on detecting a memory access to a target memory address, the processor logs into the first trace information usable to obtain a memory value corresponding to the particular memory address from the memory snapshot(s) stored within the second trace. This includes logging the particular memory address, as well as CCP message(s) indicating at least of: (i) that none of a plurality of processing units possessed a first cache line within the cache that overlaps with the target memory address; (ii) that a first processing unit initiated a cache miss for the target memory address; or (iii) that the first processing unit obtained, from a second processing, a second cache line within the cache that overlaps with the target memory address.

Abstract: Diffing subject and comparison traces. A first call tree representing function calls made by a first executable entity is created based on subject trace, and a second call tree representing function calls made by a second executable entity is created based on a comparison trace. A differencing tree is created from the call trees, with differencing tree nodes indicate a differencing status between the first and second call trees. A differencing cost is assigned to each differencing tree node, based at least on the nodes' differencing status. A differencing tree node is identified based on following nodes that most contribute to differences between the first and second call trees, and it is used to provide an indicia of a difference between the first and second function calls.

Abstract: Reducing overheads of recording a replayable execution trace of a program's execution at a computer processor by omitting logging of accesses to memory addresses whose values can be reconstructed or predicted. A computer system determines that memory values corresponding to a range of memory addresses within a memory space for a process can be obtained separately from the process' execution, and configures a data structure for instructing a processor to omit logging of memory accesses when the processor accesses an address within this range while executing the process. Correspondingly, upon detecting a memory access while executing the process, the processor determines if it has been instructed to omit logging of the access by checking the data structure. When the data structure instructs the processor to omit logging of the access, the processor omits logging the memory access while it uses a cache to process the memory access.

Abstract: Exposing a memory cell value during trace replay prior to an execution time at which the memory cell value was recorded into a trace. A computer system identifies a first and a second trace fragment within a trace, each recording an uninterrupted consecutive execution of a plurality of executable instructions. The computer system determines that the first trace fragment is orderable prior to the second trace fragment and, based on an inter-fragment analysis, that a value of a memory cell recorded into the second trace fragment is compatible with the first trace fragment. The computer system generates output data indicating that the value of the memory cell can be exposed, during a replay of the trace, at a first execution time that is prior to a second execution time of an event that caused the value of the memory cell to be recorded into the second trace fragment.