Abstract: Based on replay of a thread, one implementation observes an influx of a value of a memory cell comprising an interaction between the thread and the value of the memory cell at an execution time point in the replaying, and determines whether the value of the memory cell observed from the influx is inconsistent with a prior value of the memory cell as known by the thread at the execution time point. If so, this implementation initiates an indication of a data inconsistency. Based on replay of a plurality of threads, another implementation identifies a memory cell that was accessed by a first thread while a thread synchronization mechanism was active on the first thread. Then, if there was another access to the memory cell by a second thread without use of the thread synchronization mechanism, this implementation initiates an indication of a potential data contention.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: Exposing a memory cell value during trace replay prior to an execution time at which the memory cell value was recorded into a trace. A computer system identifies a trace fragment that records an uninterrupted consecutive execution of executable instructions. Based on performing an intra-fragment analysis of the trace fragment, the computer system determines that a memory cell value recorded into the trace fragment is compatible with memory access(es) to the memory cell that occurred during recording, prior to an event that caused the memory cell value to be recorded. The computer system determines that the memory cell value can be exposed, during trace replay, at a first execution time that is prior to a second execution time corresponding to the event that caused the value to be recorded, and generates output data indicating that the memory cell value can be exposed at the first execution time during trace replay.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: This disclosure relates to the use of execution traces to process queries against objects over their lifetime. Embodiments identify, from a trace, a memory-backed object that existed during a prior execution of an entity. A handle for logically representing memory covered by the object over the object's lifetime is identified. A plurality of associations that are represented by the handle are identified. These associations identify memory addresses that were covered by the object over its lifetime. Each association represents at least (i) a memory address that was covered by the object during its lifetime, and (ii) an execution time during the object's lifetime at which the memory address was covered by the object. A query is processed against the handle. The query includes a query based on an execution time, and processing the query includes comparing the execution time in the query to execution time(s) represented in the associations.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: Treating main memory as a collection of tagged cache lines for trace logging. A computer system allocates a plurality of memory blocks, and a corresponding plurality of tags, within a main memory. Each tag indicates whether data stored in a corresponding memory block has been captured by an execution trace. The computer system synchronizes these tags with tags in a memory cache and manages a traced status of the memory blocks. This can include one or more of (i) setting a tag to indicate a memory block has not been captured based on identifying a direct memory access operation, (ii) setting a tag based on whether a paged-in value of a memory block has been captured, (iii) setting a tag or memory categorization based whether a memory block has been initialized, or (iv) setting a tag or memory categorization based whether a memory block is mapped to a file.

Abstract: Cache-based trace logging using tags in system memory. A processor influxes a cache line into a first cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in system memory and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line has been previously captured by a trace has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: Exposing a memory cell value during trace replay prior to an execution time at which the memory cell value was recorded into a trace. A computer system identifies a trace fragment that records an uninterrupted consecutive execution of executable instructions. Based on performing an intra-fragment analysis of the trace fragment, the computer system determines that a memory cell value recorded into the trace fragment is compatible with memory access(es) to the memory cell that occurred during recording, prior to an event that caused the memory cell value to be recorded. The computer system determines that the memory cell value can be exposed, during trace replay, at a first execution time that is prior to a second execution time corresponding to the event that caused the value to be recorded, and generates output data indicating that the memory cell value can be exposed at the first execution time during trace replay.

Abstract: During an execution of a first executable entity, a computer system determines that a target chunk of executable instructions is to be recorded during the execution. Prior to executing the target chunk of executable instructions, the computer system identifies one or more input(s) of the target chunk of executable instructions, and adjusts a page table entry to cause a page fault based on an access by a second executable entity to a first memory page that corresponds to an identified input, and/or an access by the first executable entity to a second memory page that does not correspond to any identified input. Based on detecting an occurrence of a page fault during an execution of the target chunk of executable instructions, the computer system detects that there an interference with an identified input by the second executable entity and/or an incompleteness of the identified inputs.

Abstract: Recording a trace of code execution using reference bits in a processor cache. A computing device comprises processing units and a shared cache. The shared cache includes a plurality of cache lines that is each associated with a plurality of accounting bits, which each includes a reference bits portion. Stored control logic uses these reference bits to log a second read operation by a second processing unit in reference to an already logged first read operation by a first processing unit.

Abstract: Modifying a trace to expose memory cell values prior to execution times corresponding to events that caused the memory cell values to be recorded. A computer system accesses a trace that represents prior execution of one or more threads and identifies a plurality of data packets that each represents a corresponding memory cell value read from a particular memory cell. The computer system selects a particular memory cell value represented in one of the data packets. The computer system modifies the trace by removing all but one of the data packets from at least one trace fragment, or by inserting data into the trace that exposes the selected particular memory cell value at an execution time during trace replay that is prior to execution times of the execution events corresponding to the data packets and removing the data packets from the trace.

Abstract: Performing a targeted partial recording of an executable entity includes executing the executable entity at a processor. While executing the executable entity, it is determined that a target chunk of executable instructions are to be executed as part of the execution of the executable entity. Each input to the target chunk of executable instructions is identified, including identifying at least one non-parameter input. A corresponding value for each identified input is recorded into a trace, along with information identifying the target chunk of executable instructions.

Abstract: Diffing subject and comparison traces. A first call tree representing function calls made by a first executable entity is created based on subject trace, and a second call tree representing function calls made by a second executable entity is created based on a comparison trace. A differencing tree is created from the call trees, with differencing tree nodes indicate a differencing status between the first and second call trees. A differencing cost is assigned to each differencing tree node, based at least on the nodes' differencing status. A differencing tree node is identified based on following nodes that most contribute to differences between the first and second call trees, and it is used to provide an indicia of a difference between the first and second function calls.

Abstract: Transforming input data to enable execution of second executable code using trace data gathered during execution of first executable code. A trace of an execution of the first code is accessed. The trace stores data of an input that was consumed by first executable instructions of the first code. It is determined that the stored data of the input is usable as an input to second executable instructions of the second code. A difference in size/format of the stored data as used by the first instructions, compared to an input size/format expected by the second executable instructions, is identified. Based on the identified difference, a data transformation is determined that would enable the second instructions to consume the stored data. Execution of the second instructions is emulated using the stored data, including projecting the data transformation to enable the second instructions to consume the stored data.

Abstract: Expressly turning tracing on and off at each juncture between code that a developer wants to have traced and other code may reduce trace file size but adds computational cost. Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. The amount of extra tracing is balanced against the reduction in trace enablement/disablement operations by tuning thresholds, based on information about routine size and computational cost.

Abstract: Diffing subject and comparison traces. The subject and comparison traces can be matched based on identifying similar work being performed by their represented entities. The diffing includes identifying first function calls from the subject trace and identifying second function calls the comparison trace. First and second call trees are created from these function calls; parent-to-child node relationships in the call trees represent caller-to-callee function relationships. A differencing tree is created from the call trees; differencing tree nodes indicate a differencing status between the first and second call trees, and a differencing cost based on the nodes' differencing status pus an aggregation of the node's descendants' differencing costs. A differencing tree node is identified based on following nodes that most contribute to differences between the first and second call trees, and it is used to provide an indicia of a difference between the first and second function calls.

Abstract: Diffing a plurality of subject replayable traces against a plurality comparison replayable traces includes identifying first mappings among sections of consecutive instructions recorded in the subject traces, identifying distinct subject sections within the subject traces, identifying second mappings among sections of consecutive instructions recorded in the comparison traces, and identifying a plurality of distinct comparison sections within the comparison traces. Each distinct subject section is compared against distinct comparison section(s) to determine a comparison status of each distinct subject section, including whether each distinct subject section is equal to a corresponding distinct comparison section, or different than the distinct comparison sections.

Abstract: A processor records a trace of execution of an execution entity, including recording initial processor register state into the trace. The recorded initial processor register state includes a value of at least one register of a plurality of registers. Subsequent to recording initial processor register state, and based on detection of a cache miss during execution of the execution entity, the processor records an influx of data imported into the processor cache in response to the cache miss. Also subsequent to recording initial processor register state, and based on execution of a non-deterministic processor instruction of the execution entity, the processor records at least one side effect of an access to at least one model-specific register, including recording a change in the value of the at least one register of the plurality of registers. The change results from the execution of the non-deterministic processor instruction of the execution entity.

Abstract: Based on replay of a thread, one implementation observes an influx of a value of a memory cell comprising an interaction between the thread and the value of the memory cell at an execution time point in the replaying, and determines whether the value of the memory cell observed from the influx is inconsistent with a prior value of the memory cell as known by the thread at the execution time point. If so, this implementation initiates an indication of a data inconsistency. Based on replay of a plurality of threads, another implementation identifies a memory cell that was accessed by a first thread while a thread synchronization mechanism was active on the first thread. Then, if there was another access to the memory cell by a second thread without use of the thread synchronization mechanism, this implementation initiates an indication of a potential data contention.