Abstract: Recording a trace of code execution using reserved cache lines in a cache. A computing device comprises processing units and a cache. The cache includes a first plurality of cache lines that each comprise an address portion for storing a memory address within the memory device, and a value portion for storing a value associated with the memory address. The cache also includes a second plurality of reserved cache lines that store a plurality of sets of accounting bits. Each set of accounting bits comprises a plurality of accounting bits and is associated with a different cache line in the first cache lines. Each cache line in the second cache lines stores multiple of the sets of accounting bits. Stored control logic uses the plurality of sets of accounting bits in the second cache lines to track trace logging information for the first cache lines.

Abstract: A tracing coprocessor that records execution trace data based on a cache coherency protocol (CCP) message. The tracing coprocessor comprises logic that causes the tracing coprocessor to listen on a bus that is communicatively coupled to a primary processor that executes executable code instructions. The logic also causes the tracing coprocessor to, based on listening on the bus, identify at least one CCP message relating to activity at a processor cache. The logic also causes the tracing coprocessor to identify, from the at least one CCP message, a memory cell consumption by the primary processor. The logic also causes the tracing coprocessor to initiate logging, into an execution trace, at least a memory cell data value consumed by the primary processor in connection with execution of at least one executable code instruction.

Abstract: Utilizing diffgrams for trace indexing and replay. A subset of instructions of a trace, beginning with a first instruction and ending with a second instruction, are replayed to obtain state of one or more named resources. Based on replaying the subset of instructions, a diffgram is generated, which is structured such that addition of the diffgram at the first instruction brings the one or more named resources to the second state, and subtraction of the diffgram at the second instruction brings the one or more named resource to the first state. A pat of reaching a target instruction, the diffgram is later added at the first instruction to restore the second state at the second instruction, or subtracted at the second instruction to restore the first state of the first instruction.

Abstract: Identifying and reporting potential data inconsistencies and/or potential data contentions based on historic debugging traces. Based on replay of a thread, some implementations observe an influx of a value to a memory cell, and determine whether the value of the memory cell observed from the influx is inconsistent with a prior value of the memory cell as known by the thread. If so, these implementations can initiate an indication of a data inconsistency. Based on replay of a plurality of threads, other implementations identify a memory cell that was accessed by a first thread while a thread synchronization mechanism was active on the first thread. Then, if there was another access to the memory cell by a second thread without use of the thread synchronization mechanism, these implementations might initiate an indication of a potential data contention.

Abstract: A processor is configured to record a replay-able trace of execution of an execution entity. Based on detection of a cache miss during the execution of the execution entity, the processor records an influx of data imported into a processor cache in response to the cache miss, and sets a hardware bit on a cache line of the processor cache storing the influx of data. The hardware bit indicates that the cache line has been recorded into a trace. In addition, the processor records by recording at least one side effect of the access by the execution entity to the model-specific register.

Abstract: This disclosure relates to identifying and presenting differences between a plurality of recorded executions of an executable entity. One or more models are created over the plurality of recorded prior executions of at least a portion of an executable entity. These models include at least one of (i) a control flow model, or (ii) a data model. An anomalous model data point is identified within these models, and a first location in at least one of the plurality of recorded executions that corresponds to the anomalous model data point is identified. A second location in the at least one of the plurality of recorded executions is also identified. This second location is causal to the anomalous model data point at the first location. The identity of the first and/or second locations in the least one of the plurality of recorded executions is presented.

Abstract: A coprocessor stores at least part of an execution trace based on code execution at a primary processor. The coprocessor includes control logic that configures the coprocessor to listen to a bus that interconnects the primary processor and the coprocessor, and to receive one or more cache coherency protocol (CCP) messages from the bus (i.e., CCP message(s) sent on the bus by the primary processor, based on the primary processor having consumed data for a memory cell). Based on receiving the CCP message(s), the coprocessor initiates storing of the consumed data for the memory cell into an execution trace.

Abstract: Facilitating recording a trace of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, accounting bits for the cache line are set. Setting the accounting bits includes (i) setting the accounting bits to a reserved value when the operation is a write and tracing is disabled, (ii) setting the accounting bits to an index of the processing unit when the operation is a write and the accounting bits for the cache line are set to a value other than the index of the processing unit, or (iii) setting the accounting bits to the index of the processing unit when the operation is a read that is consumed by the processing unit and the accounting bits for the cache line are set to a value other than the index of the processing unit.

Abstract: Diffing a subject replayable trace against a comparison replayable trace includes identifying a first plurality of functions within a first sequence of instructions recorded in the subject trace, and identifying a second plurality of functions a second sequence of instructions recorded in the comparison trace. A first plurality of groups of the first plurality of functions, and a second plurality of groups of the second plurality of functions are identified. The first and second pluralities of groups are compared, including determining, based on an identity of each group, and on function(s) corresponding to the group, if each first group in the first plurality of groups is at least one of: equal to a second group in the second plurality of groups, a replacement of a second group in the second plurality of groups, deleted from the second plurality of groups, or inserted into the second plurality of groups.

Abstract: This disclosure relates to exposing memory cell values prior to execution time(s) corresponding to events that caused the memory cell values to be recorded into a trace. Trace fragments, including a first trace fragment and a second trace fragment, are identified within a trace. Each trace fragment records an uninterrupted consecutive execution of executable instructions on a corresponding thread. The first trace fragment can be ordered prior to the second trace fragment. It is determined that a memory cell value can be exposed, during replay of the second fragment, at a first execution time that is prior to a second execution time corresponding to an event that caused the memory cell value to be recorded into the trace during trace recording. Output data is generated which indicates that the memory cell value can be exposed at the first execution time during replay of the second trace fragment.

Abstract: Diffing subject and comparison traces. The subject and comparison traces can be matched based on identifying similar work being performed by their represented entities. The diffing includes identifying first function calls from the subject trace and identifying second function calls the comparison trace. First and second call trees are created from these function calls; parent-to-child node relationships in the call trees represent caller-to-callee function relationships. A differencing tree is created from the call trees; differencing tree nodes indicate a differencing status between the first and second call trees, and a differencing cost based on the nodes' differencing status pus an aggregation of the node's descendants' differencing costs. A differencing tree node is identified based on following nodes that most contribute to differences between the first and second call trees, and it is used to provide an indicia of a difference between the first and second function calls.

Abstract: Diffing a subject replayable trace against a plurality of comparison replayable traces includes identifying a set of mappings among the comparison replayable traces, each identifying corresponding comparison sections of consecutive instructions recorded in the comparison replayable traces that execute equivalently. A plurality of distinct comparison sections are identified within the comparison replayable traces. Each of a plurality of subject sections within the subject trace is compared against distinct comparison section(s) to determine a comparison status for each subject section, including whether each subject section is (i) equal to at least one corresponding distinct comparison section, or (ii) different than the distinct comparison sections.

Abstract: Diffing a subject replayable trace against a comparison replayable trace includes identifying a first plurality of functions within a first sequence of instructions recorded in the subject trace, and identifying a second plurality of functions a second sequence of instructions recorded in the comparison trace. A first plurality of groups of the first plurality of functions, and a second plurality of groups of the second plurality of functions are identified. The first and second pluralities of groups are compared, including determining, based on an identity of each group, and on function(s) corresponding to the group, if each first group in the first plurality of groups is at least one of: equal to a second group in the second plurality of groups, a replacement of a second group in the second plurality of groups, deleted from the second plurality of groups, or inserted into the second plurality of groups.

Abstract: Diffing a plurality of subject replayable traces against a plurality comparison replayable traces includes identifying first mappings among sections of consecutive instructions recorded in the subject traces, identifying distinct subject sections within the subject traces, identifying second mappings among sections of consecutive instructions recorded in the comparison traces, and identifying a plurality of distinct comparison sections within the comparison traces. Each distinct subject section is compared against distinct comparison section(s) to determine a comparison status of each distinct subject section, including whether each distinct subject section is equal to a corresponding distinct comparison section, or different than the distinct comparison sections.

Abstract: Modifying a trace to expose memory cell values prior to execution times corresponding to events that caused the memory cell values to be recorded. A computer system accesses a trace that represents prior execution of one or more threads and identifies a plurality of data packets that each represents a corresponding memory cell value read from a particular memory cell. The computer system selects a particular memory cell value represented in one of the data packets. The computer system modifies the trace by removing all but one of the data packets from at least one trace fragment, or by inserting data into the trace that exposes the selected particular memory cell value at an execution time during trace replay that is prior to execution times of the execution events corresponding to the data packets and removing the data packets from the trace.

Abstract: Tentatively executing an entity includes identifying a runtime data element used by the entity, the runtime data element having a first value at a particular point based on a trace of a prior execution of the entity. Input specifying a second, different, value for the runtime data element is received. A tentative replay of the entity is performed, the tentative replay applying the second, different, value for the runtime data element using the trace. The tentative replay includes setting the runtime data element to the second value and emulating one or more memory writes performed by the entity during the tentative replay. Based on determining that the entity has requested data from the trace during the tentative replay that is not available in the trace, it is detected that the tentative replay has deviated from the prior execution and can no longer continue using the trace.

Abstract: Methods and systems are disclosed for logging trace data generated by executing program code at an instruction level. In aspects, high volumes of trace data are generated during certain time periods, e.g., immediately following a start of the tracing. Processors operating at normal speeds are often unable to log such high volumes of trace data. The issue of such high volumes of trace data may be addressed by selectively and dynamically controlling logging of outstanding trace data. For example, a rate of generating the trace may be reduced by slowing processor speeds, logging of outstanding trace data may be suspended for a period, and logging of non-urgent trace data may be selectively delayed.

Abstract: Efficient register breakpoint checks rely on initiating an event based on an access to a register. Initiating the event can include, based on decoding a machine code instruction, identifying one or more registers that a machine code instruction could touch, and inserting an identification of the touched registers into a stream of executable operations for the machine code instruction. Then, while executing the executable operations, these registers can be compared with a register breakpoint collection. An event can be generated when one of these registers is in the register breakpoint collection. The event might trigger a conditional analysis, an execution break, and/or logging. In some implementations, the event might enable lifetime and/or taint analysis by removing a register from a monitoring collection if the executable operations write to the register, or by adding a destination of a read to the monitoring collection if the executable operations read from the register.

Abstract: A computing device includes processing units and a shared processor cache. Each cache line is associated with a different plurality of accounting bits, including a unit bit associated with each processing unit. An operation by a particular processing unit on a particular cache line is identified. If the operation is a read consumed by that processing unit, and when a unit bit for that processing unit in the accounting bits associated with the particular cache line is not set, at least the value portion of the particular cache line is stored or referenced in the trace, and the particular unit bit is set. If the operation is a write, each unit bit in the accounting bits associated with the cache line that are associated with any processing unit other than the particular processing unit is cleared, and the particular unit bit associated with the particular processing unit is set.

Abstract: Embodiments relate to a virtualization layer capturing replayable execution traces of VMs managed by the virtualization layer. Execution tracing can be performed on any unit of execution managed by the virtualization layer, e.g., threads, processes, virtual processors, individual VMs, multiple VMs, etc. Traced execution units may be executing in parallel. Execution tracing involves capturing to a buffer: executed instructions, memory inputted to instructions, memory outputted by instructions, registers touched by instructions, and ordering markers. Trace data can be captured in chunks, where causality is preserved and ordering is preserved between chunks but not necessarily within chunks. The chunks may be delineated by inserting monotonically increasing markers between context switches, thus relatively ordering the chunks. Determinism may be partially provided by identifying non-deterministic events. VM tracing may be transparent to guest software, which need not be instrumented.