Abstract: A single-ended to differential converter includes a converter input, a first converter output, a second converter output, and an internal node, wherein the first converter output and the second converter output comprise a differential output; a non-inverting amplifier having an input coupled to the converter input, and an output coupled to the first converter output; an inverting amplifier having an input coupled to the first converter output, and an output coupled to the second converter output; a charge pump having a charge pump output capacitor coupled between the second converter output and the internal node; and a feedback capacitor coupled between the first converter output and the internal node.

Abstract: In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.

Abstract: An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

Abstract: A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

Abstract: A single-ended to differential converter includes a converter input, a first converter output, a second converter output, and an internal node, wherein the first converter output and the second converter output comprise a differential output; a non-inverting amplifier having an input coupled to the converter input, and an output coupled to the first converter output; an inverting amplifier having an input coupled to the first converter output, and an output coupled to the second converter output; a charge pump having a charge pump output capacitor coupled between the second converter output and the internal node; and a feedback capacitor coupled between the first converter output and the internal node.

Abstract: In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.

Abstract: A microphone includes an amplifier coupled to an input node of the microphone; a shock detector coupled to the input node of the microphone; and a recovery circuit having an input coupled to an output of the shock detector, and an output coupled to the input of the microphone.

Abstract: An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

Abstract: A microphone includes an amplifier coupled to an input node of the microphone; a shock detector coupled to the input node of the microphone; and a recovery circuit having an input coupled to an output of the shock detector, and an output coupled to the input of the microphone.

Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter- leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

Abstract: According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.

Abstract: Methods and apparatuses are provided wherein a sensor which comprises at least two electrodes and a movable part is alternately biased with at least two different voltages.

Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.

Abstract: Methods and apparatuses are provided wherein a sensor which comprises at least two electrodes and a movable part is alternately biased with at least two different voltages.

Abstract: According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.

Abstract: Methods and apparatuses are provided wherein a sensor which comprises at least two electrodes and a movable part is alternately biased with at least two different voltages.

Abstract: According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.

Abstract: System and method for detecting a glitch is disclosed. An embodiment comprises increasing a bias voltage of a first capacitor, sampling an input signal of a first plate of the first capacitor with a time period, mixing the input signal with the sampled input signal, and comparing the mixed signal with a reference signal.

Abstract: System and method for detecting a glitch is disclosed. An embodiment comprises increasing a bias voltage of a first capacitor, sampling an input signal of a first plate of the first capacitor with a time period, mixing the input signal with the sampled input signal, and comparing the mixed signal with a reference signal.