Patents by Inventor Joseph F. Ahadian

Joseph F. Ahadian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6605992
    Abstract: A system of connecting errors in the control loop using multiple additional loops. A first loop carries out control in a desired way, and the additional loops are provided for the purpose of determining a specified error value. That specified error value may be, for example, a quiescent current. The specified error value is then used to correct for errors in the first loop.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventor: Joseph F. Ahadian
  • Publication number: 20030109142
    Abstract: An integrated photodetector means for controlling the output of a light source, where the control means is a photodetector formed on a silicon-on-insulator substrate. The integrated photodetector senses the optical power from the light source and provides an electrical feedback signal which can be used to adjust the DC bias levels of the light source control driver circuit. The approach readily lends itself to large arrays of light sources bonded to silicon-on-sapphire driver circuits and is especially suitable for controlling light sources such as VCSELs in arrays such as are found in communications systems.
    Type: Application
    Filed: June 24, 2002
    Publication date: June 12, 2003
    Inventors: James S. Cable, Man W. Wong, Michael A. Stuber, Charles B. Kuznia, Joseph F. Ahadian
  • Publication number: 20030034836
    Abstract: A system of connecting errors in the control loop using multiple additional loops. A first loop carries out control in a desired way, and the additional loops are provided for the purpose of determining a specified error value. That specified error value may be, for example, a quiescent current. The specified error value is then used to correct for errors in the first loop.
    Type: Application
    Filed: June 5, 2001
    Publication date: February 20, 2003
    Inventor: Joseph F. Ahadian
  • Patent number: 6512861
    Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device may be flip-bonded directly to an integrated circuit using solder bump technology. The integrated circuit then flip-bonded or wire-bonded to a BGA package. The package has alignment rails or balls and V-grooves to anchor the alignment rails/balls to align the BGA package to the PCB. The BGA package is bonded to the PCB using solder reflow technology.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: January 28, 2003
    Assignee: Intel Corporation
    Inventors: Kishore K. Chakravorty, Ian A. Young, Joseph F. Ahadian, Johanna Marie Swan
  • Publication number: 20030002770
    Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens attached to it to facillitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a BGA package. The BGA package is bonded to the PCB using solder reflow technology.
    Type: Application
    Filed: May 30, 2002
    Publication date: January 2, 2003
    Inventors: Kishore K. Chakravorty, Johanna Swan, Brandon C. Barnett, Joseph F. Ahadian, Thomas P. Thomas, Ian Young
  • Publication number: 20020196997
    Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device may be flip-bonded directly to an integrated circuit using solder bump technology. The integrated circuit then flip-bonded or wire-bonded to a BGA package. The package has alignment rails or balls and V-grooves to anchor the alignment rails/balls to align the BGA package to the PCB. The BGA package is bonded to the PCB using solder reflow technology.
    Type: Application
    Filed: June 26, 2001
    Publication date: December 26, 2002
    Inventors: Kishore K. Chakravorty, Ian A. Young, Joseph F. Ahadian, Johanna Marie Swan
  • Patent number: 6455398
    Abstract: In a method for bonding a silicon substrate to a III-V material substrate, a silicon substrate is contacted together with a III-V material substrate and the contacted substrates are annealed at a first temperature that is above ambient temperature, e.g., at a temperature of between about 150° C. and about 350° C. The silicon substrate is then thinned. This bonding process enables the fabrication of thick, strain-sensitive and defect-sensitive optoelectronic devices on the optimum substrate for such, namely, a thick III-V material substrate, while enabling the fabrication of silicon electronic devices in a thin silicon layer, resulting from the thinned Si substrate, that is sufficient for such fabrication but which has been thinned to eliminate thermally-induced stress in both the Si and III-V materials. The III-V material substrate thickness thereby provides the physical strength of the composite substrate structure, while the thinned silicon substrate minimizes stress in the composite structure.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: September 24, 2002
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Joanna M. London, Joseph F. Ahadian