Abstract: A method of forming a memory device with a laterally-recessed free layer includes forming a bottom electrode above an electrically conductive structure embedded within an interconnect dielectric material. A magnetic tunnel junction stack is formed above the bottom electrode. Forming the magnetic tunnel junction stack includes forming a magnetic reference layer above the bottom electrode, forming a tunnel barrier layer above the magnetic reference layer, and forming a magnetic free layer above the tunnel barrier layer. Opposed lateral portions of the magnetic free layer are recessed, and sidewall spacers are formed on the recessed opposed lateral portions of the magnetic free layer for confining an active region of the memory device formed by the magnetic free layer and the tunnel barrier layer.

Abstract: A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel junction stack located above the bottom electrode is formed by a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a laterally-recessed magnetic free layer above the tunnel barrier layer. Sidewall spacers surround the laterally-recessed magnetic free layer for confining an active region formed by the laterally-recessed magnetic free and the tunnel barrier layer.

Abstract: Method and a magnetoresistive random access memory (MRAM) structure is provided. The structure includes an interconnect and a multilayered magnetic tunnel junction (MTJ) pillar located on the interconnect and having an outermost sidewall. The MTJ pillar includes an electrode layer electrically connecting the MTJ pillar to the interconnect. The electrode layer includes an insulative material at an outermost portion of the electrode layer and a conductive material at a first inner portion of the electrode layer disposed radially inward from the outermost portion of the electrode layer.

Abstract: Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a metal line layer and a top via layer that each include a plurality of alternating first layers composed of a first metal and second layers composed of a second metal, whereby the second layers are thinner than the first layers.

Abstract: Embodiments of the invention are directed to a structure comprising a magnetic tunnel junction (MTJ) element and an etched bottom electrode (BE) communicatively coupled to the MTJ element. The etched BE includes a substantially non-planar BE sidewall.

Abstract: A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

Abstract: A memory device includes a bottom electrode having an uppermost surface, a first sidewall, and a second sidewall. The memory device further includes a dielectric layer covering the uppermost surface and the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode. The memory device further includes a metal body in direct contact with the uppermost surface of the bottom electrode and extending through the dielectric layer to the uppermost surface of the dielectric layer. The memory device further includes a memory component arranged in direct contact with the metal body and with the uppermost surface of the dielectric layer.

Abstract: An MRAM device is provided. The MRAM device includes a first electrode, an MRAM stack formed on the first electrode, a hardmask structure formed on the MRAM stack, and a second electrode formed on the hardmask structure. A width of an upper portion of the hardmask structure is less than a width of the MRAM stack.

Abstract: A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.

Abstract: Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.

Abstract: A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.

Abstract: A semiconductor structure includes a substrate. A first metallization layer is disposed on the substrate. A second metallization layer is disposed on the first metallization layer and having one or more openings, wherein at least one of the one or more openings is configured to expose a top surface of the first metallization layer. A polymer-adhering liner layer is disposed on sidewalls of the at least one of the one more openings in the second metallization layer. A dielectric polymer is disposed in the at least one of the one or more openings in the second metallization layer and on the polymer-adhering liner layer. The dielectric polymer is configured to seal an air gap in the dielectric polymer.

Abstract: A pillar bump structure, and a method for forming the same includes forming, on a semiconductor substrate, a blanket liner followed by a seed layer including a noble metal. A first photoresist layer is formed directly above the seed layer followed by the formation of a first plurality of openings within the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form first pillar bumps. The first photoresist layer is removed from the semiconductor structure followed by removal of portions of the seed layer extending outward from the first pillar bumps, a portion of the seed layer remains underneath the first pillar bumps.

Abstract: A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel junction stack located above the bottom electrode is formed by a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a laterally-recessed magnetic free layer above the tunnel barrier layer. Sidewall spacers surround the laterally-recessed magnetic free layer for confining an active region formed by the laterally-recessed magnetic free and the tunnel barrier layer.

Abstract: A pillar bump structure, and a method for forming the same includes forming, on a semiconductor substrate, a blanket liner followed by a seed layer including a noble metal. A first photoresist layer is formed directly above the seed layer followed by the formation of a first plurality of openings within the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form first pillar bumps. The first photoresist layer is removed from the semiconductor structure followed by removal of portions of the seed layer extending outward from the first pillar bumps, a portion of the seed layer remains underneath the first pillar bumps.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.