Abstract: An interconnect structure of an integrated circuit (IC) in which dielectric material defines upper and lower cavities and a via cavity communicative with the upper and lower cavities at upper and lower ends thereof. The interconnect structure includes first conductive material filling the upper and lower cavities to form upper and lower lines, respectively and second conductive material filling the via cavity from the upper end thereof to the lower end thereof to form a via electrically communicative with the upper and lower lines.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: An interconnect structure of an integrated circuit (IC) in which dielectric material defines upper and lower cavities and a via cavity communicative with the upper and lower cavities at upper and lower ends thereof. The interconnect structure includes first conductive material filling the upper and lower cavities to form upper and lower lines, respectively and second conductive material filling the via cavity from the upper end thereof to the lower end thereof to form a via electrically communicative with the upper and lower lines.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: Devices and methods that can facilitate hybrid sidewall barrier and low resistance interconnect components are provided. According to an embodiment, a device can comprise a first interconnect material layer that can have a first opening that can comprise a first discontinuous barrier liner coupled to first sidewalls of the first opening and a first continuous barrier layer coupled to the first discontinuous barrier liner and the first sidewalls. The device can further comprise a second interconnect material layer coupled to the first interconnect material layer, the second interconnect material layer can have a second opening that can comprise a second discontinuous barrier liner coupled to second sidewalls of the second opening, a second continuous barrier layer coupled to the second discontinuous barrier liner and the second sidewalls.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: A semiconductor structure includes a substrate. A first metallization layer is disposed on the substrate. A second metallization layer is disposed on the first metallization layer and having one or more openings, wherein at least one of the one or more openings is configured to expose a top surface of the first metallization layer. A polymer-adhering liner layer is disposed on sidewalls of the at least one of the one more openings in the second metallization layer. A dielectric polymer is disposed in the at least one of the one or more openings in the second metallization layer and on the polymer-adhering liner layer. The dielectric polymer is configured to seal an air gap in the dielectric polymer.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: A method for making a semiconductor structure includes forming a metallization layer on a substrate. The method further includes forming a dielectric layer on the metallization layer. The method further includes forming one or more openings in the dielectric layer and the metallization layer exposing a top surface of the substrate. The method further includes forming a polymer-adhering liner layer on sidewalls of the dielectric layer in the one or more openings. The method further includes selectively depositing a dielectric polymer in at least a top portion of the one or more openings and on the polymer-adhering liner layer. The dielectric polymer seals an air gap positioned between a bottom surface of the dielectric polymer and a top surface of the substrate.

Abstract: A method for making a semiconductor structure includes forming a metallization layer on a substrate. The method further includes forming a dielectric layer on the metallization layer. The method further includes forming one or more openings in the dielectric layer and the metallization layer exposing a top surface of the substrate. The method further includes forming a polymer-adhering liner layer on sidewalls of the dielectric layer in the one or more openings. The method further includes selectively depositing a dielectric polymer in at least a top portion of the one or more openings and on the polymer-adhering liner layer. The dielectric polymer seals an air gap positioned between a bottom surface of the dielectric polymer and a top surface of the substrate.

Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.

Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.

Abstract: Integrated circuits including metal-insulator-metal capacitors (MIMCAPs) generally include a diffusion barrier layer on the top and bottom surfaces of the electrode and a self-formed oxide layer on sidewalls of the electrode. The diffusion barrier layers and the self-formed oxide layers on the sidewalls of the electrode prevent diffusion of the metal defining the electrode into the interlayer dielectric. Also described are processes for fabricating the MIMCAPs.

Abstract: A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: Devices and methods that can facilitate hybrid sidewall barrier and low resistance interconnect components are provided. According to an embodiment, a device can comprise a first interconnect material layer that can have a first opening that can comprise a first discontinuous barrier liner coupled to first sidewalls of the first opening and a first continuous barrier layer coupled to the first discontinuous barrier liner and the first sidewalls. The device can further comprise a second interconnect material layer coupled to the first interconnect material layer, the second interconnect material layer can have a second opening that can comprise a second discontinuous barrier liner coupled to second sidewalls of the second opening, a second continuous barrier layer coupled to the second discontinuous barrier liner and the second sidewalls.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: A method which exploits the benefits of a seed enhancement layer (in terms of void-free copper fill), while preventing copper volume loss during planarization, is provided. The method includes forming a partial seed enhancement liner in a lower portion of an opening that contains a recessed copper portion. Additional copper is formed in the upper portion of the opening providing a copper structure in which no copper volume loss at the uppermost interface of the copper structure is observed.