Patents by Inventor Joseph F. Maniscalco

Joseph F. Maniscalco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027829
    Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Joseph F. Maniscalco, Andrew Tae Kim, Baozhen Li, Chih-Chao Yang
  • Publication number: 20200020577
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 16, 2020
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Publication number: 20200020581
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 16, 2020
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Patent number: 10529622
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Publication number: 20190393409
    Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Publication number: 20190371735
    Abstract: A method which exploits the benefits of a seed enhancement layer (in terms of void-free copper fill), while preventing copper volume loss during planarization, is provided. The method includes forming a partial seed enhancement liner in a lower portion of an opening that contains a recessed copper portion. Additional copper is formed in the upper portion of the opening providing a copper structure in which no copper volume loss at the uppermost interface of the copper structure is observed.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Oscar van der Straten, Joseph F. Maniscalco, Koichi Motoyama, Alexander Reznicek
  • Patent number: 10468346
    Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joseph F. Maniscalco, Andrew Tae Kim, Baozhen Li, Chih-Chao Yang
  • Publication number: 20190319088
    Abstract: Integrated circuits including metal-insulator-metal capacitors (MIMCAPs) generally include a diffusion barrier layer on the top and bottom surfaces of the electrode and a self-formed oxide layer on sidewalls of the electrode. The diffusion barrier layers and the self-formed oxide layers on the sidewalls of the electrode prevent diffusion of the metal defining the electrode into the interlayer dielectric. Also described are processes for fabricating the MIMCAPs.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, Oscar van der Straten, Chih-Chao Yang
  • Publication number: 20190311985
    Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Joseph F. Maniscalco, Andrew Tae Kim, Baozhen Li, Chih-Chao Yang
  • Patent number: 10431542
    Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20180233444
    Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 16, 2018
    Inventors: Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20180233445
    Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
    Type: Application
    Filed: December 27, 2017
    Publication date: August 16, 2018
    Inventors: Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10049980
    Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20140216342
    Abstract: An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In the disclosure, an interconnect dielectric material including an opening is placed within the multi-chambered processing system and then the interconnect dielectric material is transferred, under vacuum, to a deposition chamber in which the metal liner is deposited. The interconnect dielectric material including the metal liner is then transferred, under the same vacuum, to an annealing chamber in which a reflow anneal is performed.
    Type: Application
    Filed: September 10, 2013
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Stephan A. Cohen, Joseph F. Maniscalco
  • Patent number: 6562554
    Abstract: Acid-catalyzed positive photoresist compositions which are imageable with 193 nm radiation and are developable to form photoresist structures of high resolution and high etch resistance are enabled by the use of a combination of cyclic olefin polymer, photosensitive acid generator and a hydrophobic non-steroidal multi-alicyclic component containing plural acid labile linking groups. The cyclic olefin polymers preferably contain i) cyclic olefin units having polar functional moieties, ii) cyclic olefin units having acid labile moieties that inhibit solubility in aqueous alkaline solutions.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: May 13, 2003
    Assignee: International Business Machines Corporation
    Inventors: Pushkara Rao Varanasi, Joseph F. Maniscalco
  • Patent number: 6124074
    Abstract: Acid-catalyzed positive photoresist compositions which are imageable with 193 nm radiation and are developable to form photoresist structures of high resolution and high etch resistance are enabled by the use of a combination of cyclic olefin polymer, photosensitive acid generator and a hydrophobic non-steroidal multi-alicyclic component containing plural acid labile linking groups. The cyclic olefin polymers preferably contain i) cyclic olefin units having polar functional moieties, ii) cyclic olefin units having acid labile moieties that inhibit solubility in aqueous alkaline solutions.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: September 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: Pushkara Rao Varanasi, Joseph F. Maniscalco