Abstract: An apparatus and corresponding method are provided for regulating the voltage potential of a lithium ion battery based upon an operating range having an upper threshold (e.g., on the order of 4.2 v) and a lower threshold (e.g., on the order of 2.5 v) and for providing a reduction in dissipated power when the lithium ion battery is charging and when a load is drawing upon the lithium ion battery. The apparatus includes a p-minus substrate and a first p-channel enhancement Field Effect Transistor (FET) integrally formed on the p-minus substrate. The first p-channel enhancement FET is configured to limit charging of the lithium ion battery when the voltage potential of the lithium ion battery is greater than the upper threshold.

Abstract: A system on an integrated circuit chip for providing a digital-to-analog conversion includes a plurality of output members each providing a particular current when energized. These members may be disposed on the chip in a pair of spaced columns. First control lines in the space between the columns of output members provide a thermometer code. Second control lines in this space provide a binary code. The first and second control lines are preferably parallel to the columns. When a first one of the first control lines is energized, different ones or combinations of the second control lines provide progressive values in the output members between "0" and "15", assuming four (4) of the second control lines. Similarly, when a second one of the first control lines is additionally energized, different ones or combinations of the second control lines provide progressive values between "16" and "31" in associated output members. At the same time, the output members providing a value of "15" continue to be energized.

Abstract: In first and second modes, successive pairs of bytes, each with a suitable number (e.g. 8) of binary indications, are respectively processed in each clock cycle or clock half cycle to provide a true color. In these modes, the successive pairs of bytes may be processed in a 5,5,5, or a 5,6,5 pattern representing the primary colors for a pixel. In a third mode, the bytes may be introduced to a memory having a plurality of positions for storing individual binary combinations, which may be updated by a microprocessor, representing pseudo colors. In the third mode, a particular position in the memory is selected in accordance with the indications in each byte in each clock cycle or half cycle. In an additional mode, three successive bytes in a group may indicate the primary colors defining a true color when the fourth byte in the group provides a particular indication (e.g. 0 for all 8 binary bits).

Abstract: A comparator indicates the relative magnitudes of input and reference signals with improved immunity to noise signals. The comparator includes first and second transistors differentially connected to receive the input and reference signals. Third and fourth transistors connected in a latching relationship are responsive in first alternate half cycles of clock signals to the outputs from the first and second transistors to provide a regenerative action on these outputs. In first portions of the first alternate half cycles of the clock signals, a degenerative action is provided by fifth and sixth transistors respectively on the third and fourth transistors to prevent the third and fourth transistors from regenerating until the input difference voltage of these transistors has had time to increase relative to the input noise on these transistors. The fifth and sixth transistors may be provided with sizes corresponding to, or preferably sightly greater than, those of the third and fourth transistors.

Abstract: First circuitry on an integrated circuit chip has an input terminal, preferably the only input terminal, for receiving a voltage pulse introduced to a first terminal on the chip. The first circuitry damps the negative voltage peaks of the voltage pulse at a voltage of a first magnitude inherent in the construction of the first circuitry. A pair of input transistors in the first circuitry have dimensions to provide, at the input terminal to second circuitry, a clamping voltage of a first magnitude at a certain fraction of the power supply voltage. The first circuitry may include a closed loop servo amplifier which regulates the negative peaks of the pulse at the input terminal to the second circuitry to a value approximately equal to the voltage of the first magnitude. The second circuitry compares the negative peaks of the input voltage pulse with a voltage of a second magnitude inherent in the construction of the second circuitry to provide an output logic pulse.

Abstract: A system eliminates the adverse effects of serration and equalization pulses (periodically generated during the vertical sync interval) in regulating the frequency of horizontal sync pulses. These sync pulses provide timing information to regulate a video display. The system includes circuitry for stripping and processing the horizontal and vertical sync signals and the serration pulses from the video signals. These pulses are introduced to a first AND gate and through a first display line to an input of a second AND gate. Frequency divider output signals are introduced to the first AND gate and to a third AND gate through a second delay line having an equal delay with the first delay line. The output from the first AND gate passes to second inputs of the second and third AND gates. The second and third AND gates produce signals which represent the time difference between the sync and divider output signals and which have a maximum time difference equal to the delays of the delay lines.

Abstract: Output members in a matrix relationship having x and y inputs respectively receive signals in first and second pluralities cumulatively representing a digital value. These signals are decoded and are respectively introduced to the x and y inputs to activate a particular output member common to a selected x row and a selected y column. The output members in the preceding rows and preceding the activated output member in the selected row are also activated. Three-transistor (all of the same type) current sources provide constant currents to the activated output members. In each current source, a first transistor provides the constant current, a second transistor in each current source constitutes a switch operative in response to binary input signals, and a third transistor receives the constant current dependent upon the binary input to the second transistor.

Abstract: Input and reference voltages are respectively applied to the control elements of first and second transistors. This causes a substantially constant current to be divided between the first and second transistors in first time periods. In second time periods alternating with the first periods, the reference voltage is also applied to the control element of the first transistor to produce a current representation of the reference voltage. This causes the first and second transistors respectively to produce in the second periods voltages dependent only upon their relative characteristics. These voltages are introduced in the second periods to first and second capacitances to charge the capacitances when first switches such as transistors are closed. Subsequently in the second periods, the charges in the first and second capacitances are respectively transferred to third and fourth capacitances to charge the third and fourth capacitances.

Abstract: A plurality of members, each constructed to produce a substantially constant current when energized, are disposed electrically in a matrix defined by a plurality of rows and a plurality of columns. A plurality of signals cumulatively represent a digital value. Each of the signals has logic levels respectively coding for binary "1" and binary "0" and each has an individual binary significance. The binary signals of intermediate binary significance are decoded to activate an individual rows. The binary signals of high binary significance are decoded to activate an individual column. The member common to the activated row and the activated column then receives a substantially constant current, as do all of the members of lower binary signficance than such common member. The signals of lowest binary significance are also decoded to produce a current having a magnitude indicative of the binary value coded by such signals.

Abstract: First and second reference voltages of different value are introduced to opposite ends of a first line disposed on an IC chip and made from a suitable material (e.g. ion-implanted polysilicon). An input voltage having a value between such reference voltages is provided on a second line on the chip. The second line may be substantially parallel to the first line and made from a suitable material (e.g. polysilicon heavily implanted with ions) to provide an identical voltage at every line position. Bridging layers substantially perpendicularly disposed between the lines at progressive positions on the lines may be made from polysilicon heavily implanted with ions. The magnitudes of the line and reference voltages at each bridging layer are compared in a differential amplifier to produce a signal with a polarity dependent upon such relative magnitudes. The signals from the differential amplifiers are combined in pluralities of logical networks.

Abstract: A converter converts to an analog value a plurality of digital signals each having characteristics representing an individual digital value. A plurality of switches are disposed in sets with the switches in each set being responsive to an individual one of the digital signals. The number of switches in each set is related to the digital significance of the set, preferably on an inverse basis. The switches are connected in a repetitive array to output members and a line to provide for the connection for progressive ones of the members to the output line in accordance with the pattern of the switches in the conductive and non-conductive states in representation of progressive increases in the digital value. The repetitive also provides, with such progressive increases in the digital values, output members previously connected to the line. The repetitive array may be responsive to the digital signals in a single delay time.

Abstract: A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from MOS transistors. Circuitry provides output currents of optimal waveforms from the digital-to-analog converters for driving stages subsequent to such converters. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz). The circuits facilitate the production of the signals at such high frequencies by employing the distributed capacitances in a first transistor to expedite the response of a second transistor to binary input signals introduced to the first transistor.

Abstract: A reference generator is used in a digital-to-analog converter to provide for a replication of colors in accordance with binary information introduced to the converter. The generator is responsive to binary signals each having first and second logic levels respectively representing binary "1" and binary "0" and each representing a different one of the binary colors red, green and blue. Each of the binary signals is introduced to an individual one of transistors in a first plurality. An energizing voltage is also introduced to the transistors to obtain a flow of current through such transistors in accordance with the logic levels of such input signals and the magnitude of the energizing voltage. A substantially constant current is provided at first particular times and a reference voltage is provided at other times. An impedance may be common to the circuit for the substantially constant current and the reference voltage.

Abstract: An integrated circuit chip has circuitry for converting a binary coded value to an analog value. The chip includes first and second matrices each defined by rows and columns. The rows and columns have sources at different positions for producing currents in response to binary signals coding for the binary value. Each row in the first matrix is connected to a row in the second matrix on a reverse-image basis. For example, if each matrix has thirty two (32) rows, rows 1 and 32 in the first matrix are respectively connected to rows 32 and 1 in the second matrix. The rows in the matrices are sequentially selected in a pattern providing particular convergences and divergences of successive paris of such rows in each matrix. Such sequential selection provides progressive convergences and then progressive divergences of the rows in each of the successive pairs in each matrix about the center line as a reference. Such progressive convergences and divergences may occur in at least a pair of successive cycles.

Abstract: A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from C-MOS transistors. Circuitry is also provided for converting signal levels from TTL logic devices external to the chip into signals for operating the C-MOS transistors on the chip by adjusting the voltages from the TTL logic devices into voltages optimal for operating the C-MOS transistors. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz).

Abstract: A first semi-conductor has a first threshold voltage and provides a particular voltage drop across it in its saturated state of operation. A second semi-conductor has a second threshold voltage and provides the particular voltage drop across it in its saturated state of operation. The second semi-conductor may be a native device. The first and second semi-conductors are connected to provide a common flow of current. A current is induced, as by a third semi-conductor, to flow in the second semi-conductor. The first and second semi-conductors are commonly biased to produce a flow of saturated current through them when a current is induced to flow in the second semi-conductor. Each of the first, second and third semi-conductors may be provided with a gate, drain and source. The sources and drains of the semi-conductors may be in series.

Abstract: In a fast frame recorder having (1) a video camera adapted to produce signals corresponding to a variety of frame rates, (2) a variable speed tape recorder adapted to down-convert the frame rate of the camera signals to a reference frame rate by appropriately reducing the recorder tape speed to a reference speed, and (3) a display monitor adapted to receive the reference frame rate signals, the camera thereof may be adjusted for various scene and frame rate conditions without need to record the camera frame rate signals (for purposes of signal down-conversion). This is, in accordance with the invention, achieved by selecting a certain line (or lines) from each frame of the camera output signal, and applying such selected lines directly to the display monitor. Skipping from line to line in the camera output signal has the effect of down-converting the frame rate of the camera output signal as required.

Abstract: The present invention provides apparatus for adjusting the time base of a signal that is read out from an addressable memory device. In accordance with a disclosed embodiment, coarse time base adjustment is provided by controlling the address count produced by a readout counter, while the phase of the counter clocking signal is adjusted to provide fine time base adjustment.

Abstract: A wideband high voltage video amplifier shares the amplification of positive and negative signal peaks between positively and negatively charging output bipolar transistors, respectively, thereby circumventing distortion of the output signal by the base-to-collector junction capacitance of each transistor.

Abstract: A video converter operating in real time that responds to frames of N lines of video data in a non-interlaced format to form two fields of interlaced data without loss of any information. The converter operates with a minimum of two lines of memory storage capacity and a minimum of timing structure. The concept in accordance with the invention allows data of substantially any non-interlaced format to be converted for display on an interlaced display unit such as a standard TV system.