Patents by Inventor Joseph M. Jeddeloh

Joseph M. Jeddeloh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for memory hub-based expansion bus
    Patent number: 8117371
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: February 14, 2012
    Assignee: Round Rock Research, LLC
    Inventor: Joseph M. Jeddeloh
  • SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS
    Publication number: 20120005389
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Joseph M. Jeddeloh
  • System for controlling memory accesses to memory modules having a memory hub architecture
    Patent number: 8086815
    Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 27, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Joseph M. Jeddeloh, Terry R. Lee
  • APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM
    Publication number: 20110314199
    Abstract: A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 22, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Joseph M. Jeddeloh
  • Memory arbitration system and method having an arbitration packet protocol
    Patent number: 8082404
    Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: December 20, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Jeddeloh, Ralph James
  • MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM
    Publication number: 20110296227
    Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 1, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Joseph M. Jeddeloh, James B. Johnson
  • METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES
    Publication number: 20110271158
    Abstract: A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • RECONFIGURABLE MEMORY MODULE AND METHOD
    Publication number: 20110246743
    Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Terry R. Lee, Joseph M. Jeddeloh
  • System and method for memory hub-based expansion bus
    Patent number: 8019924
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: September 13, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Joseph M. Jeddeloh
  • MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION
    Publication number: 20110219196
    Abstract: A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 8, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Joseph M. Jeddeloh
  • Memory system and method using stacked memory device dice, and system using the memory system
    Patent number: 8010866
    Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: August 30, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Joseph M. Jeddeloh, James B. Johnson
  • Method and apparatus for testing high capacity/high bandwidth memory devices
    Patent number: 7979757
    Abstract: A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: July 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES
    Publication number: 20110164446
    Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Terry R. Lee, Joseph M. Jeddeloh
  • METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE
    Publication number: 20110167238
    Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Joseph M. Jeddeloh, Terry R. Lee
  • Apparatus and method for direct memory access in a hub-based memory system
    Patent number: 7966430
    Abstract: A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 21, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Joseph M. Jeddeloh
  • Reconfigurable memory module and method
    Patent number: 7966444
    Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: June 21, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Terry R. Lee, Joseph M. Jeddeloh
  • SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS
    Publication number: 20110145463
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 16, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Joseph M. Jeddeloh
  • System and method for on-board timing margin testing of memory modules
    Patent number: 7958412
    Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 7, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Joseph M. Jeddeloh
  • Memory hub with internal cache and/or memory access prediction
    Patent number: 7945737
    Abstract: A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 17, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Joseph M. Jeddeloh
  • MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES
    Publication number: 20110113189
    Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Joseph M. Jeddeloh