Abstract: A header of a combine harvester includes a belt conveyor configured to direct a movement of harvested crop material toward a feederhouse of the combine harvester. The belt conveyor is located adjacent an inlet of the feederhouse. The belt conveyor includes at least one protrusion extending radially from the belt conveyor that helps direct movement of harvested crop material toward the feederhouse.

Abstract: A header of a combine harvester includes an auger for directing a movement of harvested crop material toward a feederhouse of the combine harvester. The auger includes multiple protrusions configured to both extend from and retract into the auger during rotation of the auger to assist movement of the harvested crop material toward the feederhouse.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: A header includes a belt conveyor configured to direct a movement of harvested crop material toward a feederhouse of the combine harvester. The belt conveyor is located adjacent an inlet of the feederhouse. The belt conveyor includes at least one protrusion extending radially from the belt conveyor that helps direct movement of harvested crop material toward the feederhouse.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

Abstract: Various examples described herein are directed to systems and methods for generating a financial account statement. First financial data associated with a first financial account statement for a customer is received. Second financial data associated with a second financial account statement for the customer is received. The first financial data may be from an earlier financial account statement. Changes between the first financial data and the second financial data are determined. Highlighted changes to augment based on preferences of the customer and the determined changes are determined. Content associated with the highlighted changes is determined. The second financial account statement is created based on the second financial data. The content associated with the highlighted changes is linked in the second financial account statement.

Abstract: A manufacturing process adopting the reconfigurable robotic manufacturing cells that can work conjointly and yet have the capabilities to be reconfigured to disconnect from other cells and handle multiple tasks. The reconfigurable robotic cell is not dependent on any other robotic cells to complete work in progress.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings.

Abstract: A header of a combine harvester is provided. The header includes an auger for directing a movement of harvested crop material toward a feederhouse of the combine harvester. The auger includes multiple protrusions configured to both extend from and retract into the auger during rotation of the auger to assist movement of the harvested crop material toward the feederhouse.

Abstract: A header of a combine harvester is provided. The header includes a belt conveyor configured to direct a movement of harvested crop material toward a feederhouse of the combine harvester. The belt conveyor is located adjacent an inlet of the feederhouse. The belt conveyor includes at least one protrusion extending radially from the belt conveyor that helps direct movement of harvested crop material toward the feederhouse.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

Abstract: An adjustable and maneuverable taxidermy stand may include a base assembly; a lower hinge assembly adjustably attached to the base assembly; an upper hinge assembly pivotally attached to the lower hinge assembly; a hub assembly adjustably attached to the upper hinge assembly; and at least one mounting plate assembly adjustably attached to the hub assembly. Each assembly may be attached to an adjacent assembly using a shaft collar subassembly. Each shaft collar subassembly may include a threaded collar half removably attached to a non-threaded collar half; and a fastener attaching the threaded collar half to the non-threaded collar half, wherein when the threaded collar half is attached to the non-threaded collar half an inner diameter of the shaft collar subassembly is sized to accommodate a shaft tubing from any of the various assemblies.