Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: A ferroelectric memory and a method for operating a ferroelectric memory are disclosed. The ferroelectric memory includes a ferroelectric memory cell having a ferroelectric capacitor characterized by a maximum remanent charge, Qmax. A write circuit receives a data value having more than two states for storage in the ferroelectric capacitor. The write circuit measures Qmax for the ferroelectric capacitor, determines a charge that is a fraction of the measured Qmax to be stored in the ferroelectric capacitor, the fraction being determined by the data value. The write circuit causes a charge equal to the fraction times Qmax to be stored in the ferroelectric capacitor. A read circuit determines a value stored in the ferroelectric capacitor by measuring a charge stored in the ferroelectric capacitor, measuring Qmax for the ferroelectric capacitor, and determining the data value from the measured charge and the measured Qmax.

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes having a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.