Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

Abstract: An improved ferroelectric capacitor exhibiting reduced imprint effects in comparison to prior art capacitors. A capacitor according to the present invention includes top and bottom electrodes and a ferroelectric layer sandwiched between the top and bottom electrodes, the ferroelectric layer comprising a perovskite structure of the chemical composition ABO.sub.3 wherein the B-site comprises first and second elements and a dopant element that has an oxidation state greater than +4. The concentration of the dopant is sufficient to reduce shifts in the coercive voltage of the capacitor with time. In the preferred embodiment of the present invention, the ferroelectric element comprises Pb in the A-site, and the first and second elements are Zr and Ti, respectively. The preferred dopant is chosen from the group consisting of Niobium, Tantalum, and Tungsten. In the preferred embodiment of the present invention, the dopant occupies between 1 and 8% of the B-sites.

Abstract: A method for making an improved LSCO stack in the generation of platinum features on the surface of a substrate. The method provides an inexpensive means for depositing and etching LSCO material in the construction of small platinum features. The method comprises sputtering of the LSCO material and utilizing a photoresist mask to pattern the LSCO in accordance with the platinum features. The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.

Abstract: A method for fabricating an integrated circuit having at least one integrated circuit component fabricated in a silicon substrate and a second device that is to be fabricated on a silicon oxide layer that covers the integrated circuit component. The integrated circuit component has a terminal that is to be connected a corresponding terminal on the second device. The second device includes an electrode structure in contact with a dielectric component that includes a layer of ferroelectric material. In the method of the present invention, a boundary layer comprising non-conducting polysilicon is deposited over the silicon oxide layer. The electrode structure is then fabricated by depositing one or more layers over the boundary layer. The ferroelectric layer is then deposited over the electrode structure and etched to provide the dielectric component. The boundary layer is then removed utilizing an etchant that etches silicon oxide much slower than polysilicon.

Abstract: An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively.

Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

Abstract: A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier above the surface of the substrate for preventing the materials of the ferroelectric capacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Abstract: A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO.sub.2 or Si.sub.3 N.sub.4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond the bottom electrode to the substrate surface.

Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. The resulting structure may be heated in the presence of oxygen to temperatures in excess of 800.degree. C. without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.

Abstract: A non-volatile memory circuit comprises cross-coupled transistors which drive first and second nodes to differential voltage states. First and second ferroelectric capacitors are connected respectively between the first and second nodes and a common node. The ferroelectric capacitors are set to opposite polarization states as a function of the voltage states at the first and second differential nodes. When power is lost from the circuit, the last data state in the circuit is stored in the ferroelectric capacitors. When power is restored to the memory circuit, the ferroelectric capacitors unbalance the differential nodes to such an extent to cause the circuit to become reestablished to the last data state stored in the circuit. An input signal can be received at one of the nodes through an input transistor to set the state of the memory circuit and the state of the circuit can be read from one of the nodes through an output transistor. The input and output transistors can be the same device.

Abstract: The sensing array detects an image by measuring the changes in the dielectric constant of individual capacitors in a rectangular array of capacitors. The present invention avoids the use of isolation transistors to eliminate the effects of other capacitors in the array when measuring the capacitance of a given capacitor in the array. During the measurement of any given capacitor in the array, the present invention maintains a zero potential difference across the capacitors that are not being measured, thereby eliminating any interference that might be caused by these capacitors.

Abstract: Devices for converting digital data into a light pulse train and decoding such a pulse train are disclosed. The light pulse generating device generates a train of light pulses having a pattern determined by a numerical value represented by a plurality of binary bits. The light pulse train generating device stores the bits in a register. Each cell of the register is connected to a light switching device that will interrupt a first light beam in response to a light signal if the value stored in the cell is a logical one. If the value is a logical 0, the interruption will not occur. The decoding device utilizes a plurality of light activated switches to route individual pulses in the light pulse train to different photodetectors. The light activated switching devices avoid the delays inherent in electrically activated switching devices.

Abstract: An improved method for making aluminum connections to platinum electrodes is described. The method utilizes an oxide layer to isolate the aluminum from the platinum. The oxide layer is created by ashing the surface of the platinum using an Oxygen plasma.

Abstract: An improved method for constructing integrated circuit structures in which a buffer SiO.sub.2 layer is used to separate various components comprising ferroelectric materials or platinum is disclosed. The invention prevents interactions between the SiO.sub.2 buffer layer and the ferroelectric materials. The invention also prevents the cracking in the SiO.sub.2 which is commonly observed when the SiO.sub.2 layer is deposited directly over a platinum region on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material and which is also an electrical insulator to separate the SiO.sub.2 layer from the ferroelectric material and/or the platinum regions.

Abstract: An improved ferroelectric structure and the method for making the same is disclosed. The improved structure reduces the fatigue problems encountered in ferroelectric capacitors while providing avoiding problems in depositing the ferroelectric material which have prevented other solutions to the fatigue problem from being effective. The improved ferroelectric structure also provides improved adhesion to the underlying substrate. The ferroelectric structure has a bottom electrode comprising a layer of PtO.sub.2 which is generated by depositing a layer of Platinum on a suitable substrate and then exposing the Platinum layer to an Oxygen plasma. The ferroelectric material is then deposited on the PtO.sub.2 layer.

Abstract: An improved memory device based on a non-volatile variable resistance element is disclosed. The resistive element is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferro-electric layer. The semiconductor forms one plate of a parallel plate capacitor having a dielectric comprising the ferro-electric layer. The state of the memory device is determined by measuring the resistivity of the semiconductor layer between two contacts on the semiconductor layer. The state of polarization of the ferro-electric layer is altered by applying a voltage between one of these contacts and the other plate of the capacitor.

Abstract: A light activated AND gate is disclosed which generates a light signal at a first output port in response to the simultaneous presence of light signals at an input port and a control port. With a light signal present at the control port, a light beam at the input port is reflected from an interface between two regions having different indices of refraction, and the reflected light beam then exits through a first output port. In the absence of a light signal at the control port, the two regions of the switching device have the same index of refraction, and the light beam at the input port passes through both regions and exits through a second output port.

Abstract: A light activated switching device is disclosed in which the receipt of a light signal is used to switch a light beam between two output ports. The input light beam is reflected from an interface between two regions having different indices of refraction when the light signal is present. The reflected light beam then exits through the first output port. In the absence of the light signal, the two regions have the same index of refraction, and the light beam passes through both regions and exits through the second output port.

Abstract: An improved non-volatile variable resistance element is disclosed. The resistive element is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferroelectric layer.

Abstract: An improved read/write optical disk is disclosed which is capable of being rewritten more than 10.sup.6 times. The disk utilizes a storage medium in which data is stored as different polarization states in the same phase of the material. The preferred embodiment utilizes a lead lanthanum zirconate titanate material for the storage medium. The state of polarization of the material at the location of a specified data bit is changed by applying a voltage to the bit location in question. The location is specified by illuminating the surface of the disk with light in the infra-red.