Abstract: The disclosed subject matter relates generally to structures in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a structure for use in a conductive line. The present disclosure also relates to a method of forming the structures. The present disclosure provides a structure in a semiconductor device, the structure having a corrugated surface on at least one of its sides. The disclosed structures may have smaller or no micro-trenches and may therefore increase the breakdown voltage of the structures.

Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

Abstract: A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.

Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Abstract: A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

Abstract: A device may include a first conductive element and an interlevel dielectric arranged over the first conductive element. The device may further include a dual damascene opening including a first end, a second end, and sidewalls extending between the first and second ends, the sidewalls extending through the interlevel dielectric. A metal-insulator-metal (MIM) stack may line the dual damascene opening. The MIM stack may include a first conductive liner lining the sidewalls and the second end of the dual damascene opening, an insulator layer lining the first conductive liner, and a second conductive liner lining the insulator layer. A first metal interconnect may be disposed in and filling the dual damascene opening lined with the MIM stack.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.

Abstract: A resistive memory device is provided. The resistive memory device comprises a first metal oxide layer above a body electrode. A correlated electron layer located between a source and a drain and above the first metal oxide layer. A gate above a bottom portion of the correlated electron layer.

Abstract: A memory device may be provided. The memory device may include a substrate, wherein the substrate includes a well having a first conductivity type. The memory device may further include a contact element arranged in the well and including a first contact having the first conductivity type; a diode layer arranged in the well and having a second conductivity type opposite to the first conductivity type; and a dummy gate configured to isolate the first contact from the diode layer. The memory device may further include a memory element electrically connected to the diode layer.

Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.

Abstract: A resistive memory device is provided. The resistive memory device comprises a first electrode and a resistive layer over the first electrode, the resistive layer having a sidewall. A second electrode is over the resistive layer. An insulating liner is formed on the sidewall of the resistive layer. The insulating liner comprises two layers of different dielectric materials.

Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.

Abstract: A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.

Abstract: The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. More particularly, the present disclosure relates to a method of forming a sensor device and a bond pad in the same dielectric region. The present disclosure also relates to the semiconductor devices formed by the method disclosed herein.

Abstract: A memory device may be provided. The memory device may include a first electrode including a first side surface and a second side surface opposite to the first side surface; a passivation layer arranged laterally alongside the first side surface of the first electrode; a switching layer arranged laterally alongside the passivation layer; and a second electrode arranged along the switching layer.