Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.

Abstract: A device for isolating a microbe or a virion includes a semiconductor substrate; and a trench formed in the semiconductor substrate and extending from a surface of the semiconductor substrate to a region within the semiconductor substrate; wherein the trench has dimensions such that the microbe or the virion is trapped within the trench.

Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layer. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which comprise an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure comprises a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

Abstract: A device for isolating a microbe or a virion includes a semiconductor substrate; and a trench formed in the semiconductor substrate and extending from a surface of the semiconductor substrate to a region within the semiconductor substrate; wherein the trench has dimensions such that the microbe or the virion is trapped within the trench.

Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.