Patents by Inventor Judson R. Holt

Judson R. Holt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Asymmetric semiconductor device and method of forming same
    Patent number: 10049942
    Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony I. Chou, Judson R. Holt, Arvind Kumar, Henry K. Utomo
  • Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same
    Patent number: 10020307
    Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
  • STRAIN RETENTION SEMICONDUCTOR MEMBER FOR CHANNEL SiGe LAYER OF pFET
    Publication number: 20180190768
    Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.
    Type: Application
    Filed: December 20, 2017
    Publication date: July 5, 2018
    Inventors: Dina H. Triyoso, Timothy J. McArdle, Judson R. Holt, Amy L. Child, George R. Mulfinger
  • Forming zig-zag trench structure to prevent aspect ratio trapping defect escape
    Patent number: 9947532
    Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
  • FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH
    Publication number: 20180097113
    Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: ERIC C. HARLEY, JUDSON R. HOLT, YUE KE, RISHIKESH KRISHNAN, KEITH H. TABAKMAN, HENRY K. UTOMO
  • Junction butting structure using nonuniform trench shape
    Patent number: 9923082
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 20, 2018
    Assignee: GLOBAL FOUNDRIES INC.
    Inventors: Anthony I. Chou, Judson R. Holt, Arvind Kumar, Henry K. Utomo
  • FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
    Patent number: 9917190
    Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Keith H. Tabakman, Henry K. Utomo
  • Recess liner for silicon germanium fin formation
    Patent number: 9893154
    Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy J. McArdle, Judson R. Holt, Junli Wang
  • Self-aligned sacrificial epitaxial capping for trench silicide
    Patent number: 9812453
    Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Lakshmanan H. Vanamurthy, Scott Beasor, Timothy J. McArdle, Judson R. Holt, Hao Zhang
  • RECESS LINER FOR SILICON GERMANIUM FIN FORMATION
    Publication number: 20170294515
    Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 12, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Timothy J. MCARDLE, Judson R. HOLT, Junli WANG
  • Buffer layer for modulating Vt across devices
    Patent number: 9722045
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 1, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt
  • SEMICONDUCTOR MANUFACTURED NANO-STRUCTURES FOR MICROBE OR VIRUS TRAPPING OR DESTRUCTION
    Publication number: 20170191106
    Abstract: A method includes disposing a solution including a microbe or a virion on a surface of a semiconductor substrate, the semiconductor substrate having a trench extending from the surface to a region within the semiconductor substrate; wherein the the microbe or the virion is trapped within the trench of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 6, 2017
    Inventors: Yann Astier, David Esteban, Judson R. Holt, Henry K. Utomo
  • SEMICONDUCTOR MANUFACTURED NANO-STRUCTURES FOR MICROBE OR VIRUS TRAPPING OR DESTRUCTION
    Publication number: 20170191913
    Abstract: A device for isolating a microbe or a virion includes a semiconductor substrate; and a trench formed in the semiconductor substrate and extending from a surface of the semiconductor substrate to a region within the semiconductor substrate; wherein the trench has dimensions such that the microbe or the virion is trapped within the trench.
    Type: Application
    Filed: April 29, 2016
    Publication date: July 6, 2017
    Inventors: Yann Astier, David Esteban, Judson R. Holt, Henry K. Utomo
  • Semiconductor manufactured nano-structures for microbe or virus trapping or destruction
    Publication number: 20170191912
    Abstract: A device for isolating a microbe or a virion includes a semiconductor substrate; and a trench formed in the semiconductor substrate and extending from a surface of the semiconductor substrate to a region within the semiconductor substrate; wherein the trench has dimensions such that the microbe or the virion is trapped within the trench.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 6, 2017
    Inventors: Yann Astier, David Esteban, Judson R. Holt, Henry K. Utomo
  • SEMICONDUCTOR MANUFACTURED NANO-STRUCTURES FOR MICROBE OR VIRUS TRAPPING OR DESTRUCTION
    Publication number: 20170189570
    Abstract: A device for isolating a microbe or a virion includes a semiconductor substrate; and a trench formed in the semiconductor substrate and extending from a surface of the semiconductor substrate to a region within the semiconductor substrate; wherein the trench has dimensions such that the microbe or the virion is trapped within the trench.
    Type: Application
    Filed: April 29, 2016
    Publication date: July 6, 2017
    Inventors: Yann Astier, David Esteban, Judson R. Holt, Henry K. Utomo
  • Recess liner for silicon germanium fin formation
    Patent number: 9698226
    Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy J. McArdle, Judson R. Holt, Junli Wang
  • JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE
    Publication number: 20170179257
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 22, 2017
    Inventors: Anthony I. Chou, Judson R. Holt, Arvind Kumar, Henry K. Utomo
  • SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF FABRICATING SAME
    Publication number: 20170179127
    Abstract: An aspect of the disclosure includes a semiconductor structure comprising: a set of fins on a substrate, the set of fins including a relaxed silicon germanium layer; and a dielectric between each fin in the set of fins; wherein each fin in a n-type field effect transistor (nFET) region further includes a strained silicon layer over the relaxed silicon germanium layer of each fin in the nFET region; wherein each fin in a p-type field effect transistor (pFET) region further includes a strained silicon germanium layer over the relaxed silicon germanium layer of each fin in the pFET region.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Judson R. Holt, Jody A. Fronheiser, Kangguo Cheng, Shogo Mochizuki, Stephen W. Bedell
  • ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE
    Publication number: 20170148661
    Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Judson R. Holt, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
  • BUFFER LAYER FOR MODULATING Vt ACROSS DEVICES
    Publication number: 20170117387
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.
    Type: Application
    Filed: October 23, 2015
    Publication date: April 27, 2017
    Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt