Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.

Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width.

Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

Abstract: Disclosed herein are related to an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.

Abstract: A memory device includes a plurality of bit lines, a plurality of word lines, and a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines. Each of the bit cells is configured to present an initial logic state on the bit lines. A power supply terminal is coupled to the memory cell array. A controller is coupled to the word lines and the bit lines, and is configured to, during a RNG phase, precharge the bit lines to a second voltage level lower than a first voltage level, and determine the initial logic states of the plurality of bit cells to generate a random number. The first voltage level is a voltage level for operating the memory cell array during an SRAM phase.

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.