Abstract: A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.

Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

Abstract: An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.

Abstract: A method comprises selecting a memory cell included in a memory cell array in which data is to be stored. The memory cell array is connected with a logic gate array. The memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output. The method also comprises communicating a write row output signal to the logic gate array. The write row output signal is communicated from a write address row decoder to the logic gate array. The write address row decoder has a plurality of write row outputs coupled with the logic gate array. The method further comprises communicating a write column output signal to the logic gate array. The write column output signal is communicated from a write address column decoder to the logic gate array.

Abstract: An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.

Abstract: An integrated circuit that includes an array of memory cells. The integrated circuit also includes a write address row decoder having a plurality of write row outputs and a write address column decoder having a plurality of write column outputs. A write logic array is electrically connected to the write row outputs and the write column outputs and has a separate write word line (WWL) output electrically connected to each cell in the array of memory cells.

Abstract: A power control device used for controlling power includes a table generating module, a detecting module, a timing module, a table search module, a determining module, a controlling module, a storage system and a processor. The table generating module is used to generating a relationship table. The detecting module is used to receive a disconnected message of the ports and the wireless transmitting units. The timing module is used to measure the disconnected time of the wireless transmitting units. The table search module is used to search personal electrical equipment from the relationship table. The determining module makes determination according to the disconnected message. The controlling module controls the electrical equipment.

Abstract: Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided.

Abstract: A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.

Abstract: A test equipment to test power over Ethernet (PoE) function of an Ethernet device comprises a first connector, a second connector, a data signal transmission circuit, a first polarity determination circuit, a second polarity determination circuit and a notification circuit. The first connector receives and transmits data signals and power signals transmitted by the Ethernet device. The data signal transmission circuit transmits the data signals to the second connector and outputs the power signals. The first and second polarity determination circuits receive and output the power signals to the notification circuit. The notification circuit receives the power signals and consequently generates a notice to indicate the PoE function of the Ethernet device is normal.

Abstract: A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.

Abstract: Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided.

Abstract: A test equipment to test power over Ethernet (PoE) function of an Ethernet device comprises a first connector, a second connector, a data signal transmission circuit, a first polarity determination circuit, a second polarity determination circuit and a notification circuit. The first connector receives and transmits data signals and power signals transmitted by the Ethernet device. The data signal transmission circuit transmits the data signals to the second connector and outputs the power signals. The first and second polarity determination circuits receive and output the power signals to the notification circuit. The notification circuit receives the power signals and consequently generates a notice to indicate the PoE function of the Ethernet device is normal.

Abstract: A method for manufacturing a sensing device, such as a bolometer device or other devices. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a first reflection layer overlying the substrate and forming a first electrode layer overlying the substrate. The method includes forming a sacrificial layer overlying a portion of the first reflection layer and a portion of the first electrode layer. The sacrificial layer is patterned using photolithography techniques. The patterned sacrificial layer corresponds to a cavity region. The method also forms a second electrode layer overlying the sacrificial layer and forms an elastic layer overlying the patterned sacrificial layer. The elastic layer encloses the cavity region corresponding to the patterned sacrificial layer. The method releases the sacrificial layer to form an opening in the cavity region.

Abstract: A 1×N2 wavelength selective switch (WSS) configuration in which switch elements are configured in a way that enables the input or output fibers to be arranged in a two-dimensional (2D) array. By employing 2D arrays of input/output channels, the channel count is increased from N to N2 for wavelength selective switches. In one embodiment, in which the components are arranged as a 2- ƒ imaging system, a one-dimensional (1D) array of mirrors is configured such that each mirror has a dual scanning axis (i.e., each mirror can be scanned in X and Y directions). In another embodiment, in which the components are arranged as a 4- ƒ imaging system, two 1D arrays of mirrors are configured with orthogonal scanning directions. In both embodiments, the number of ports is increased from N to N2.

Abstract: A 1×N2 wavelength selective switch (WSS) configuration in which switch elements are configured in a way that enables the input or output fibers to be arranged in a two-dimensional (2D) array. By employing 2D arrays of input/output channels, the channel count is increased from N to N2 for wavelength selective switches. In one embodiment, in which the components are arranged as a 2-f imaging system, a one-dimensional (1D) array of mirrors is configured such that each mirror has a dual scanning axis (i.e., each mirror can be scanned in X and Y directions). In another embodiment, in which the components are arranged as a 4-f imaging system, two 1D arrays of mirrors are configured with orthogonal scanning directions. In both embodiments, the number of ports is increased from N to N2.

Abstract: A 1×N2 wavelength selective switch (WSS) configuration in which switch elements are configured in a way that enables the input or output fibers to be arranged in a two-dimensional (2D) array. By employing 2D arrays of input/output channels, the channel count is increased from N to N2 for wavelength selective switches. In one embodiment, in which the components are arranged as a 2-f imaging system, a one-dimensional (1D) array of mirrors is configured such that each mirror has a dual scanning axis (i.e., each mirror can be scanned in X and Y directions). In another embodiment, in which the components are arranged as a 4-f imaging system, two 1D arrays of mirrors are configured with orthogonal scanning directions. In both embodiments, the number of ports is increased from N to N2.

Abstract: A 1×N2 wavelength selective switch (WSS) configuration in which switch elements are configured in a way that enables the input or output fibers to be arranged in a two-dimensional (2D) array. By employing 2D arrays of input/output channels, the channel count is increased from N to N2 for wavelength selective switches. In one embodiment, in which the components are arranged as a 2-f imaging system, a one-dimensional (1D) array of mirrors is configured such that each mirror has a dual scanning axis (i.e., each mirror can be scanned in X and Y directions). In another embodiment, in which the components are arranged as a 4-f imaging system, two 1D arrays of mirrors are configured with orthogonal scanning directions. In both embodiments, the number of ports is increased from N to N2.

Abstract: A method for manufacturing a sensing device, such as a bolometer device or other devices. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a first reflection layer overlying the substrate and forming a first electrode layer overlying the substrate. The method includes forming a sacrificial layer overlying a portion of the first reflection layer and a portion of the first electrode layer. The sacrificial layer is patterned using photolithography techniques. The patterned sacrificial layer corresponds to a cavity region. The method also forms a second electrode layer overlying the sacrificial layer and forms an elastic layer overlying the patterned sacrificial layer. The elastic layer encloses the cavity region corresponding to the patterned sacrificial layer. The method releases the sacrificial layer to form an opening in the cavity region.