Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width.

Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

Abstract: A memory circuit includes a first memory cell, a second memory cell, a pre-charge circuit and a sense amplifier. The pre-charge circuit is coupled to a first bit line and a second bit line. The pre-charge circuit is configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal. The sense amplifier is coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line. The sense amplifier is responsive to a second signal and a third signal. The second signal and the third signal being different from the first signal.

Abstract: A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.

Abstract: A memory circuit includes a first memory cell, a second memory cell, a pre-charge circuit and a sense amplifier. The pre-charge circuit is coupled to a first bit line and a second bit line. The pre-charge circuit is configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal. The sense amplifier is coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line. The sense amplifier is responsive to a second signal and a third signal. The second signal and the third signal being different from the first signal.

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

Abstract: A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.

Abstract: A memory macro includes a first input terminal, a first memory cell array, a second memory cell array, a first input output (IO) circuit, a second IO circuit, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first set of driver circuits are coupled to the first memory cell array and the first IO circuit. The second set of driver circuits are coupled to the second memory cell array and the second IO circuit. The logic circuit has a first terminal coupled to the first input terminal and configured to receive a first signal. The logic circuit is coupled to the first set of driver circuits and the second set of driver circuits. The logic circuit is configured to generate at least a second signal responsive to the first signal causing a change in the operational mode of the memory macro.

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A memory macro includes a first input terminal, a first memory cell array, a second memory cell array, a first input output (IO) circuit, a second IO circuit, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first set of driver circuits are coupled to the first memory cell array and the first IO circuit. The second set of driver circuits are coupled to the second memory cell array and the second IO circuit. The logic circuit has a first terminal coupled to the first input terminal and configured to receive a first signal. The logic circuit is coupled to the first set of driver circuits and the second set of driver circuits. The logic circuit is configured to generate at least a second signal responsive to the first signal causing a change in the operational mode of the memory macro.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells, a second row of memory cells aligned with the first row of memory cells along a predetermined direction, and a third word line and a fourth word line over and electrically coupled to the second row of memory cells. The first word line is aligned with the third word line, and the second word line is aligned with the fourth word line. One of the first word line or the second word line is electrically coupled with one of the third word line or the fourth word line. The other one of the first word line or the second word line is electrically decoupled from the other one of the third word line or fourth word line.

Abstract: A method comprises selecting a memory cell included in a memory cell array in which data is to be stored. The memory cell array is connected with a logic gate array. The memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output. The method also comprises communicating a write row output signal to the logic gate array. The write row output signal is communicated from a write address row decoder to the logic gate array. The write address row decoder has a plurality of write row outputs coupled with the logic gate array. The method further comprises communicating a write column output signal to the logic gate array. The write column output signal is communicated from a write address column decoder to the logic gate array.