Patents by Inventor Jui Liang

Jui Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9312359
    Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
  • Publication number: 20150380506
    Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
  • Publication number: 20150355734
    Abstract: An electronic system, a touch stylus and a data transmission method between an electronic apparatus and a touch stylus are disclosed herein. The data transmission method, utilized between a first electronic device and a touch stylus, includes steps of: generating movement data according to displacement of the touch stylus.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Applicant: HTC Corporation
    Inventors: Pi-Lin LO, Yi-Cheng LI, Jui-Liang CHEN, Yi-Fan HSUEH, Yen-Cheng LIN
  • Publication number: 20150349088
    Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
  • Patent number: 9196542
    Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: November 24, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin
  • Patent number: 9196500
    Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: November 24, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Po-Chao Tsao, Chia-Jui Liang, Chien-Ting Lin
  • Patent number: 9190291
    Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 17, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jui Liang, Po-Chao Tsao, Jun-Jie Wang, Chih-Sen Huang
  • Patent number: 9159798
    Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
  • Patent number: 9136348
    Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
  • Patent number: 9117925
    Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jui Liang, Po-Chao Tsao
  • Publication number: 20150194348
    Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 9, 2015
    Inventors: Chia-Jui Liang, Po-Chao Tsao
  • Patent number: 9013003
    Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jui Liang, Po-Chao Tsao
  • Publication number: 20150097248
    Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.
    Type: Application
    Filed: November 21, 2014
    Publication date: April 9, 2015
    Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
  • Publication number: 20150054751
    Abstract: A system includes a stylus including a body having an elongated portion, a tapered portion coupled to the elongated portion, and a conductive layer disposed on the elongated portion, an electronic device, a touch controller and a processing unit. The electronic device comprises a touch sensor generating a sensing signal when the touch sensor senses the conductive layer. The touch controller is coupled to the touch sensor, receives the sensing signal and generates a first signal based on the received sensing signal. The processing unit is coupled to the touch controller, receives the first signal and triggers a function of the electronic device based on the first signal.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: HTC CORPORATION
    Inventors: Ko-Hsin HSIANG, Pi-Lin LO, Peter Dao-Chun SHANN, Jui-Liang CHEN
  • Patent number: 8951918
    Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jung Li, Chia-Jui Liang, Po-Chao Tsao, Ching-Ling Lin, En-Chiuan Liou
  • Publication number: 20150011090
    Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventors: Chia-Jui Liang, Po-Chao Tsao, Jun-Jie Wang, Chih-Sen Huang
  • Patent number: 8928112
    Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
  • Patent number: 8912074
    Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.
    Type: Grant
    Filed: July 13, 2014
    Date of Patent: December 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
  • Publication number: 20140349452
    Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin
  • Publication number: 20140332920
    Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. Apart of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 13, 2014
    Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu