Abstract: The present invention relates to bifunctional compounds, which find utility as modulators of targeted ubiquitination, especially inhibitors of a variety of polypeptides and other proteins which are degraded and/or otherwise inhibited by bifunctional compounds according to the present invention. In particular, the present invention is directed to compounds, which contain on one end a VHL ligand which binds to the ubiquitin ligase and on the other end a moiety which binds a target protein such that the target protein is placed in proximity to the ubiquitin ligase to effect degradation (and inhibition) of that protein. The present invention exhibits a broad range of pharmacological activities associated with compounds according to the present invention, consistent with the degradation/inhibition of targeted polypeptides.

Abstract: A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.

Abstract: A circuit, intended to be associated in series with a load to be powered including a first field-effect transistor; at least one second field-effect transistor, associated in parallel with the first transistor; and at least one sensor of information representative of a current transmitted to said load, the gate of the second transistor being coupled to an output of the sensor.

Abstract: A field effect transistor includes a substrate; a semiconductor structure formed on a main face of the substrate, the semiconductor structure including a channel area; a first electrode and a second electrode between which extends the channel area, the first electrode including a plurality of portions spaced apart from each other, each portion of the first electrode contributing to forming an elementary transistor referred to as island; connection tracks for electrically connecting the portions of the first electrode to one another; and in which each portion of the first electrode is connected to a connection track through a fuse area, each fuse area associated with the portion of the first electrode of an island being capable of being broken in such a way as to electrically insulate said island if it is defective.

Abstract: A micro-electronic device includes a first electronic component and a second electronic component, and a substrate formed of a first semiconductor material for supporting the components. The first component and the second component each include an active layer formed at least partially from a second semiconductor material different from the first semiconductor material. The device further includes, for each of the components, a stack for maintaining electrical voltage, which stack is situated between the substrate and the active layer of the electronic component under consideration and which comprises two layers forming a junction P-N formed from the same semiconductor material as the substrate and which insulates the relevant active layer from the substrate. The assemblies respectively including the first component and the second component and their respective stack for maintaining electrical voltage are separated from each other by a barrier made of electrically insulating material.

Abstract: A method for obtaining mesas that are made at least in part of a nitride (N), the method includes providing a stack comprising a substrate and at least the following layers disposed in succession from the substrate a first layer, referred to as the flow layer, and a second, crystalline layer, referred to as the crystalline layer; forming pads by etching the crystalline layer and at least one portion of the flow layer such that: —each pad includes at least: —a first section, referred to as the flow section, formed by at least one portion of the flow layer, and a second, crystalline section, referred to as the crystalline section, framed by the crystalline layer and overlying the flow section, the pads are distributed over the substrate so as to form a plurality of sets of pads; and epitaxially growing a crystallite on at least some of said pads and continuing the epitaxial growth of the crystallites until the crystallites carried by the adjacent pads of the same set coalesce.

Abstract: A GaN-based power transistor including: a stack of layers in a vertical direction (z), the stack including, from an upper surface of the stack: a first AlGaN-based barrier), a GaN-based layer, and a second AlGaN-based barrier; and a gate pattern including: a metal gate, and a gate dielectric electrically insulating the metal gate from the stack, the metal gate being in contact with a bottom part and a wall part of the gate dielectric, the gate pattern passing through the first AlGaN-based barrier, then totally passing through the GaN-based layer and at least partially through the second AlGaN-based barrier, in the vertical direction (z), such that the second AlGaN-based barrier has a concentration of aluminium [Al]2 of less than or equal to 8% at.

Abstract: Electron gas transistor of normally open type, includes a first semiconductor layer laid out along a layer plane and a second semiconductor layer formed on the first semiconductor layer and laid out along the layer plane, the first and second semiconductor layers forming an electron gas layer at the interface thereof; a third semiconductor layer with P type doping formed on the second semiconductor layer and laid out along the layer plane, a first zone with N type doping of which a part is arranged within the thickness of the third semiconductor layer, the first zone-delimiting a source zone; a second zone with N or metal type doping having at least one part arranged in the second semiconductor layer; a source electrode formed on the source zone; a drain electrode formed on the first semiconductor layer; and a gate located between the source electrode and the second zone.

Abstract: A circuit, intended to be associated in series with a load to be powered including a first field-effect transistor; at least one second field-effect transistor, associated in parallel with the first transistor; and at least one sensor of information representative of a current transmitted to said load, the gate of the second transistor being coupled to an output of the sensor.

Abstract: A field-effect transistor includes a III-N semiconductor layer including a first face and a second face opposite the first face, the first face having a polarity of the nitrogen (N) type; a drift layer disposed on the first face of the III-N semiconductor layer; a channel layer disposed on the drift layer and forming a heterostructure with the drift layer; a gate structure extending to the drift layer through the channel layer; a source electrode disposed on the channel layer; and a drain electrode disposed on the second face of the III-N semiconductor layer.

Abstract: A JBS diode includes a substrate; a first semiconductor layer arranged on a first face of the substrate and having a first type of conductivity, the first semiconductor layer including a projecting portion delimited by a trench; a second semiconductor layer arranged on the projecting portion and having a second type of conductivity opposite to the first type of conductivity; an electrically insulating layer arranged at the bottom of the trench; a first electrode including a first portion in Schottky contact with the first semiconductor layer, the first portion being arranged on the electrically insulating layer and against a side wall of the projecting portion of the first semiconductor layer; a second portion in ohmic contact with the second semiconductor layer; a second electrode in ohmic contact with the substrate.

Abstract: An integrated electronic device includes a first terminal and a second terminal, a Schottky diode having a first threshold voltage and coupled between the first terminal and the second terminal, a derivation component having a second threshold voltage greater than the first threshold voltage and coupled between the first terminal and the second terminal. The derivation component comprises a super-junction.

Abstract: A semiconductor diode, including: a first doped semiconductor region of a first conductivity type; a second doped semiconductor region of a second conductivity type opposite to the first conductivity type, arranged on top of and in contact with the upper surface of the first semiconductor region; a first conductive region arranged on top of and in contact with the upper surface of the second semiconductor region, the first conductive region comprising a through opening opposite a portion of the second semiconductor region; a second conductive region made of a material different from that of the first conductive region, coating the upper surface of the second semiconductor region opposite said opening; a cavity extending through the second conductive region and through the second semiconductor region opposite a portion of said opening; a dielectric region coating the lateral walls and the bottom of the cavity; a third conductive region coating the dielectric region on the lateral walls and at the bottom of the

Abstract: A normally-off heterojunction field-effect transistor is provided, including a superposition of a first layer, of III-N type, and of a second layer, of III-N type, so as to form a two-dimensional electron gas; a stack of an n-doped third layer making electrical contact with the second layer, and of a p-doped fourth layer placed in contact with and on the third layer, a first conductive electrode and a second conductive electrode making electrical contact with the two-dimensional electron gas; a dielectric layer disposed against a lateral face of the fourth layer; and a control electrode separated from the lateral face of the fourth layer by the dielectric layer.

Abstract: The invention aims for a polarisation circuit of a power component comprising a capacitive dividing bridge and a resistive dividing bridge formed on the same substrate as the component. An additional electrode 1? in the front face 100 of the substrate makes it possible to adjust one of the capacitance values of the capacitive dividing bridge according to the other of the capacitance values coming from one of the electrodes of the power component. The sizing of this additional electrode furthermore makes it possible to obtain a leakage resistance contributing to the resistive dividing bridge. Alternatively, two additional resistances R, R? formed in the front face of the substrate making it possible to obtain the resistive dividing bridge independently of the capacitive dividing bridge.

Abstract: A JBS diode includes a substrate; a first semiconductor layer arranged on a first face of the substrate and having a first type of conductivity, the first semiconductor layer including a projecting portion delimited by a trench; a second semiconductor layer arranged on the projecting portion and having a second type of conductivity opposite to the first type of conductivity; an electrically insulating layer arranged at the bottom of the trench; a first electrode including a first portion in Schottky contact with the first semiconductor layer, the first portion being arranged on the electrically insulating layer and against a side wall of the projecting portion of the first semiconductor layer; a second portion in ohmic contact with the second semiconductor layer; a second electrode in ohmic contact with the substrate.

Abstract: A field effect transistor includes a substrate; a semiconductor structure formed on a main face of the substrate, the semiconductor structure including a channel area; a first electrode and a second electrode between which extends the channel area, the first electrode including a plurality of portions spaced apart from each other, each portion of the first electrode contributing to forming an elementary transistor referred to as island; connection tracks for electrically connecting the portions of the first electrode to one another; and in which each portion of the first electrode is connected to a connection track through a fuse area, each fuse area associated with the portion of the first electrode of an island being capable of being broken in such a way as to electrically insulate said island if it is defective.

Abstract: An optocoupler is provided, including at least one light source and at least one matrix of photovoltaic cells facing the at least one light source, the at least one light source being configured to receive, at an input, an input electrical signal, and to generate, at an output, according to the input electrical signal, a light signal, sent to the at least one matrix of photovoltaic cells, the at least one matrix of photovoltaic cells being configured to receive, at the input, at least partially the light signal and to deliver, at the output, at least one output electrical signal, at the level of at least two connection pads, and the at least one light source being a matrix of laser diodes.

Abstract: Electron gas transistor of normally open type, includes a first semiconductor layer laid out along a layer plane and a second semiconductor layer formed on the first semiconductor layer and laid out along the layer plane, the first and second semiconductor layers forming an electron gas layer at the interface thereof; a third semiconductor layer with P type doping formed on the second semiconductor layer and laid out along the layer plane, a first zone with N type doping of which a part is arranged within the thickness of the third semiconductor layer, the first zone-delimiting a source zone; a second zone with N or metal type doping having at least one part arranged in the second semiconductor layer; a source electrode formed on the source zone; a drain electrode formed on the first semiconductor layer; and a gate located between the source electrode and the second zone.

Abstract: An integrated electronic device includes a first terminal and a second terminal, a Schottky diode having a first threshold voltage and coupled between the first terminal and the second terminal, a derivation component having a second threshold voltage greater than the first threshold voltage and coupled between the first terminal and the second terminal. The derivation component comprises a super-junction.