Abstract: The present invention relates to a semiconductor device having an integrated metal shield. The shield, created as part of a MOSFET, is formed about a gate electrode of the MOSFET to effectively reduce drain-to-gate capacitance and increase breakdown voltage. The shield consists of a metallic shield contact via and a source contact extension. The metallic shield contact via, formed between the gate electrode and a drain region of the MOSFET, may be either a series of closely spaced vias or a wide continuous via. The metallic shield contact via is isolated from the surface of a semiconductor wafer by a shield isolation layer at one end. The metallic shield contact via is electrically coupled to the source contact extension at the other end. The source contact extension is metallic, and may be formed from the same metal used to create a source contact and a drain contact for the MOSFET.

Abstract: A flip chip power device having an integrated low inductance ground and heat sink path and an isolation structure is provided. A substrate is formed having transistors and an ohmic contact region circumscribing the transistors. Dielectric layers are formed on the substrate, and a common metal layer is formed on the dielectric layers. An isolation metal layer is formed on the dielectric layers above the ohmic contact region. The common metal layer is coupled to a first region of each of the transistors, and the isolation metal layer is coupled to the ohmic contact region. A first bump is formed on the common metal layer, and a second bump is formed on the isolation metal layer. When the power device is attached to a second substrate, the first bump forms a low inductance ground and heat sink path to the second substrate, and an isolation structure is formed.

Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

Abstract: A slap yoke clip has a side portion formed configured to fit over a side portion of a slap yoke and engage a nut of a transverse retaining bolt to retain the slap yoke clip on the slap yoke. An abutment portion of the slap yoke clip extends from the slap yoke clip side portion for abutting a surface of the slap yoke to prevent rotation of the slap yoke clip with respect to the slap yoke. An elastically deformable latch portion of the slap yoke clip extends from the slap yoke clip side portion, at an angle thereto, for elastically deforming when a steering shaft is laterally inserted into the slap yoke and for returning to a relatively undeformed condition after insertion of the steering shaft into the slap yoke to prevent exit of the steering shaft from the slap yoke.

Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

Abstract: A semiconductor component (100) includes a semiconductor substrate (16) that is formed with trench (27). A semiconductor layer (20) is formed in the trench for coupling a control signal (VB) through a sidewall (25) of the trench to route a current (Ic) through a bottom surface (23) of the trench.

Abstract: A semiconductor component (100) includes a semiconductor substrate (16) that is formed with trench(27). A semiconductor layer (20) is formed in the trench for coupling a control signal (VB) through a sidewall (25) of the trench to route a current (Ic) through a bottom surface (23) of the trench.

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: A slap yoke clip has a side portion formed configured to fit over a side portion of a slap yoke and engage a nut of a transverse retaining bolt to retain the slap yoke clip on the slap yoke. An abutment portion of the slap yoke clip extends from the slap yoke clip side portion for abutting a surface of the slap yoke to prevent rotation of the slap yoke clip with respect to the slap yoke. An elastically deformable latch portion of the slap yoke clip extends from the slap yoke clip side portion, at an angle thereto, for elastically deforming when a steering shaft is laterally inserted into the slap yoke and for returning to a relatively undeformed condition after insertion of the steering shaft into the slap yoke to prevent exit of the steering shaft from the slap yoke.

Abstract: A shaft depressor is used for seating a shaft against a closed, usually curved, portion between first and second sides of a U-shaped socket in a slap yoke of a steering shaft assembly. It is used together with a clamp bolt which extends through a hole in the first side of the socket and fastens to threads at a second parallel side thereof. The shaft depressor consists of a cylindrical body having an inside diameter sized to fit over the clamp bolt, an outside diameter sized to pass through the hole in the first side of the U-shaped socket, and projecting members for pressing the shaft into the closed portion of the socket. The shaft depressor has a tapered lead at one end for easy insertion through the hole in the first parallel side and a plurality of fins projecting radially outwardly from the surface of the cylindrical bushing. The radially projecting fins may be axially extending ridges, circumferential ridges, cones, or a single helical ridge on the surface of the cylindrical body.

Abstract: A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).