Abstract: Described herein is technology for, among other things, a method of displaying a number of views in response to user scrolling. A basic, generic view is initially rendered for display on a client. Subsequent views are rendered for display that tracks the scrolling. During the scrolling process, data is not requested from the server. Only data that is stored on the client device is used while scrolling. When the scrolling has deemed to have stopped, the client requests additional data from the server. This additional data is rendered for display and is also stored in the locally on the client. Subsequent views containing this data can be generated quickly because the data exists locally. Thereby, views can be quickly and smoothly scrolled through and will appear richer in content over time.

Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.

Abstract: A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.

Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: A ceramic honeycomb structure comprised of at least two separate smaller ceramic honeycombs that have been adhered together by a cement comprised of inorganic fibers and a binding phase wherein the smaller honeycombs and fibers are bonded together by the binding phase which is comprised of an amorphous silicate, aluminate or alumino-silicate glass and the cement has at most about 5% by volume of other inorganic particles. The cement may be made in the absence of other inorganic and organic additives while achieving a shear thinning cement, for example, by mixing oppositely charged inorganic binders in water together so as to make a useful cement for applying to the smaller honeycombs to be cemented.

Abstract: An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.

Abstract: An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.

Abstract: An apparatus (100) for supporting workpieces thereon includes a seat (10), a holding board (20), and a magnetic module connecting the seat to the holding board. The magnetic module (70) includes a first member (40) secured in the seat and a second member (50) secured in the holding board. The first member and the second member cooperate to provide a magnetic force thereby detachably fixing the holding board to the seat.

Abstract: Embodiments disclosed herein describe an isolated switched-mode power supply with its output regulated from the primary side, by generating a sensing current using a sensing element coupled to the output of the power supply, and measuring a scaled version of the sensing current which depends on the output voltage, and calculating an estimate voltage representing the output voltage, and regulating the output of the isolated switched-mode power supply based on the estimate voltage.

Abstract: Embodiments disclosed herein describe a switched-mode power supply with the EMI isolated from a input power, by disconnecting the input power from the switched-mode power supply when the switched-mode power supply is switching.

Abstract: The present teachings relate to solid oxide fuel cells with internal reforming capability. The solid oxide fuel cell generally includes a cathode, an electrolyte, an anode, and a catalyst layer in contact with the anode. The catalyst layer can include a support membrane and a reforming catalyst layer associated with the support membrane. In some embodiments, the reforming catalyst can include one or more partial oxidation reforming catalysts. The present teachings also provide methods of making and operating the solid oxide fuel cells described above.

Abstract: The present teachings relate to an electrochemical system including an electrochemical device and multiple independent circuits which permit independent control of the reaction rates at different sections of the electrochemical device. The electrochemical device can be a fuel cell or an electrolyzer, and can include a common electrode in electrical communication with two or more independent circuits. The present teachings also relate to operating methods of the electrochemical system described.

Abstract: An integral engine component is disclosed. The integral engine component may have a solid first member and a second member cast in place relative to the solid first member. A metallurgical bond may exist between the solid first member and the second member, and the melting temperature of the solid first member may be lower than the melting temperature of the second member.

Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Abstract: A method of forming gray iron components includes applying a substantially uniform magnetic field to gray iron. The method also includes heat-treating the gray iron while the gray iron is within the magnetic field.

Abstract: Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.