Abstract: The information transfer method includes: determining an indicator of a start bit in a protection time slot or a preamble time slot of a laser, and establishing a communication channel according to the indicator of the start bit; inserting Operation Administration and Maintenance (OAM) information of a Long Reach-Passive Optical Network (LR-PON) device into an upstream frame sent to an Optical Line Terminal (OLT) device by the LR-PON device at a position indicated by the indicator of the start bit, and transporting the upstream frame to the OLT device through the communication channel. Therefore, OAM functions of the LR-PON device are extended, so that the OAM information can be transported by the LR-PON device independently, and OAM characteristics of the LR-PON device are enhanced. For example, PON protection is better supported, and the speed and success ratio of protection switching of a PON system are increased.

Abstract: A semiconductor device can include a drift region, at least a portion of the drift region located laterally between a drain region and a source region. The drift region can include a first layer having a first doping concentration and a second layer having a second higher doping concentration than the first layer. The second layer of the drift region be configured to allow drift current between the source region and the drain region when a depletion region is formed in at least a portion of the first layer between the source region and the drain region.

Abstract: An apparatus (100) for supporting workpieces thereon includes a seat (10), a holding board (20), and a magnetic module connecting the seat to the holding board. The magnetic module (70) includes a first member (40) secured in the seat and a second member (50) secured in the holding board. The first member and the second member cooperate to provide a magnetic force thereby detachably fixing the holding board to the seat.

Abstract: An integrated circuit includes current mode drivers that provide equalized outputs. A parallel-to-serial converter circuit receives data at less than one fourth the output data rate, and provides main data and equalization data at one fourth the output data rate to at least one four-to-one multiplexer. The main data and equalization data is multiplexed onto an output node at the output data rate.

Abstract: An apparatus is provided that relates to an electrochemical cell assembly. The apparatus is capable of controlling water loss from a fuel cell, at least in part by separating gas and liquid fluid flows. A variety of flow designs are provided that separate liquid electrolyte flow from reagent gas flow. Some flow designs may be suitable for one or more of fuel cells, rechargeable fuel cells, and batteries such as metal hydride batteries. Furthermore, some embodiments may include a single electrochemical cell, or plurality of cells arranged in parallel or in series. Some embodiments may also relate to methods of mitigating water loss from an electrochemical cell assembly.

Abstract: An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.

Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Abstract: Embodiments disclosed herein describe a network device including a class AB common mode suppression (CMS) circuit coupled in parallel between a line voltage source and a physical layer (PHY) device that provides active EMI suppression and Phy device termination. A network connector is coupled to provide the line voltage source to the class AB CMS circuit. The class AB CMS circuit provides current to the PHY device, terminates open-drain transmit drivers of the PHY device and suppresses common mode noise thereby minimizing electromagnetic interference. In other embodiments, the class AB CMS circuit is coupled in parallel between the network connector and a physical layer (PHY) device. The class AB CMS circuit suppresses common mode noise, and terminates open-drain transmit drivers of the PHY device, thereby minimizing electromagnetic interference.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Abstract: The present teachings relate to an electrochemical system including an electrochemical device and multiple independent circuits which permit independent control of the reaction rates at different sections of the electrochemical device. The electrochemical device can be a fuel cell or an electrolyzer, and can include a common electrode in electrical communication with two or more independent circuits. The present teachings also relate to operating methods of the electrochemical system described.

Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

Abstract: Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.

Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: An electroerosion control system includes a general CNC controller being configured for controlling a general CNC machine process, a power supply for energizing a tool electrode and a workpiece to be machined, an electroerosion controller electrically connecting with the power supply for controlling an output of the power supply, and adaptively and electrically connecting with the general CNC controller for communication thereof, and a sensor sensing real-time status information of a working gap between the tool electrode and the workpiece and for sending said real-time status information to said electroerosion controller. Said electroerosion controller automatically controls the electroerosion machining process through the general CNC controller according to the real-time status information of the working gap.

Abstract: An electroerosion spindle assembly includes a main shaft, a tool electrode having a rear end directly or indirectly attached to the shaft and in alignment with the main shaft in a longitudinal direction, a container surrounding the main shaft, a stationary-to-rotary electrical conduction device mounted on the container for transitting power energy to the tool electrode, and a channel routing a flushing fluid to a front end of the tool electrode. The channel has at least one flushing slot in the container.

Abstract: A semiconductor device including: a low threshold PMOS device formed over an N-type region, the source and drain of the low threshold PMOS formed in P-regions surrounded by N-regions; a low threshold NMOS device formed in a P-type region, the source and drain of the low threshold NMOS formed in N-regions surrounded by P-regions; first and second substrate bias generators, each connected to one of the low threshold devices for generating a substrate bias; a voltage source for generating substrate bias during a standby mode to reduce leakage current; wherein a low voltage threshold is established by the source and drain regions of the low threshold devices and their respective surrounding regions of opposite polarity.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.