Abstract: Methods, systems, and devices for logical selector gate programming are described. A memory architecture may include a stack of materials that form memory cells at multiple levels in the stack of materials. A portion of the memory cells may be organized into a block that includes a quantity of sub-blocks, each sub-block being independently accessible from other sub-blocks. The memory architecture may include a quantity of bit lines extending through the stack of materials, and a bit line contact coupling a subset of the bit lines with supporting circuitry. In some cases, each bit line of the subset may correspond to a respective sub-block. In some cases, the stack of materials may include one or more levels configured to provide different voltage thresholds for each bit line of the subset, where each bit line of the subset is selectable based on the different voltage thresholds.

Abstract: Methods, systems, and devices for selector for vertical planar cell and in-pillar cell structures are described. Memory cell channels may be independently selectable when coupled with a common bit line contact. The memory cell channels may be formed in a stack of materials and within a memory slot or a memory pillar. The memory cell channels may be independently selectable based one or more implantation regions, a staircase formation, or both.

Abstract: Methods, systems, apparatuses, and devices for vertical planar cells with in-pillar channel structures are described. The described techniques provide for memory cell channels to be formed relatively close to other memory cell channels within a portion of a stack of materials. For example, the described techniques support forming recesses within a pillar or slot and forming memory cell channels within respective recesses, such that a separation material prevents or mitigates interference from a memory cell channel in an adjacent recess. In some examples, a cavity may grant access to an adjacent slot or pillar such that notches of separation material may be formed to separate memory cell channels within the slot or pillar.

Abstract: Methods, systems, and devices for p-type and n-type doping of a backside source for memory channels within an apparatus are described. An apparatus may be formed with both an n-type doped region and a p-type doped region coupled with a backside source. The two doped regions may support current generation for both erase and program operations, providing for reliable and efficient memory access operations. The doped regions may be separated from one another by the plug that protects the memory cells and other regions of the apparatus from diffusion during a backside source formation process. That is, the conductive plug may be formed and may be doped with opposite charges on opposite ends of the conductive plug before a backside source is subsequently formed and coupled with the two doped regions. The opposite ends of the conductive plug may be doped with opposite charges.

Abstract: Arrays of memory cells including a plurality of strings of series-connected memory cells, a data line, a common source, and a conductive element between the data line and the common source, wherein the conductive element has a first side facing the common source and a second side facing the data line. Each of the strings of series-connected memory cells including a respective first subset of memory cells of a respective plurality of memory cells between the first side of the conductive element and the common source, and selectively connected to the conductive element on the first side of the conductive element. Each of the strings of series-connected memory cells including a respective second subset of memory cells of its respective plurality of memory cells between the second side of the conductive element and the data line.

Abstract: Arrays of memory cells including a data line, a common source, a conductive element between the data line and the common source, a first string of series-connected memory cells having a first segment of series-connected memory cells selectively connected to the conductive element and a second segment of series-connected memory cells selectively connected to the conductive element and selectively connected to its first segment of series-connected memory cells through the conductive element, and a second string of series-connected memory cells having a first segment of series-connected memory cells selectively connected to the conductive element and a second segment of series-connected memory cells selectively connected to the conductive element and selectively connected to its first segment of series-connected memory cells through the conductive element, as well as apparatus containing such arrays of memory cells and methods of their operation, and methods of their formation.

Abstract: A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

Abstract: A transistor includes a source, a drain, a gate layer, an undoped or lightly doped channel layer, and a gate dielectric layer. The undoped or lightly doped channel layer extends between the source and the drain. The channel layer includes at least one heavily doped region to distribute channel potential along the channel layer. The gate dielectric layer is between the gate layer and the channel layer.

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

Abstract: A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a first field-effect transistor between the data line and a first string of series-connected memory cells, and a second field-effect transistor between the data line and a second string of series-connected memory cells, wherein a control gate of the first field-effect transistor is connected to a control gate of the second field-effect transistor, and wherein a channel of the first field-effect transistor was fabricated to have a first threshold voltage and a channel of the second field-effect transistor was fabricated to have a second threshold voltage, different than the first threshold voltage.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

Abstract: Apparatus might include a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors, wherein the plurality of series-connected first field-effect transistors are configured to store user data, and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

Abstract: Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove

Abstract: Arrays of memory cells including a data line, a common source, a conductive element between the data line and the common source, a first string of series-connected memory cells having a first segment of series-connected memory cells selectively connected to the conductive element and a second segment of series-connected memory cells selectively connected to the conductive element and selectively connected to its first segment of series-connected memory cells through the conductive element, and a second string of series-connected memory cells having a first segment of series-connected memory cells selectively connected to the conductive element and a second segment of series-connected memory cells selectively connected to the conductive element and selectively connected to its first segment of series-connected memory cells through the conductive element, as well as apparatus containing such arrays of memory cells and methods of their operation, and methods of their formation.