Patents by Inventor Jun Fujiki
Jun Fujiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10090319Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type; a stacked body; a plurality of columnar portions; a plurality of first insulating portions having a wall configuration; and a plurality of second insulating portions having a columnar configuration. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body and a charge storage film. The first insulating portions extend in the stacking direction and in a first direction crossing the stacking direction. The second insulating portions extend in the stacking direction. A wide of the second insulating portions along a second direction crossing the first direction in a plane is wider than a wide of the first insulating portions along the second direction. The second insulating portions are disposed in a staggered lattice configuration.Type: GrantFiled: September 7, 2016Date of Patent: October 2, 2018Assignee: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai
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Publication number: 20180247951Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: ApplicationFiled: August 31, 2017Publication date: August 30, 2018Applicant: Toshiba Memory CorporationInventors: Kotaro FUJII, Jun FUJIKI, Shinya ARAI
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Publication number: 20180118938Abstract: An object of the present invention is to provide a resin composition having excellent heat resistance and excellent thermal adhesiveness, so as to provide an electric insulating sheet having excellent heat resistance. In order to achieve the aforementioned object, the present invention provides a resin composition which contains a polyether sulfone resin and a resin having a specific melt viscosity, and contains at least a phenoxy resin other than the polyether sulfone resin.Type: ApplicationFiled: November 22, 2016Publication date: May 3, 2018Applicant: Nitto Shinko CorporationInventors: Yasuyuki Kihara, Takahiro Sakaguchi, Jun Fujiki
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Patent number: 9931812Abstract: There is provided insulating paper for oil-immersed motors used in an oil-immersed motor in a state where folding is applied to the paper, the motor operating in a state where it is immersed in a cooling oil, the paper including a polyester film and heat resistant sheets made from aromatic polyamide laminated to both front and back surfaces of the polyester film, the polyester film and the heat resistant sheets being bonded with an acrylic adhesive, wherein the acrylic adhesive contains polyisocyanate and a polybutyl acrylate having a weight average molecular weight of 400,000 or more in a proportion of the polyisocyanate of more than 3 parts by weight and 20 parts by weight or less based on 100 parts by weight of the polybutyl acrylate.Type: GrantFiled: December 27, 2012Date of Patent: April 3, 2018Assignee: NITTO SHINKO CORPORATIONInventors: Yasuo Kashiwagi, Yoshiki Takahashi, Yoshihide Kitagawa, Jun Fujiki
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Patent number: 9917098Abstract: One embodiment includes a plurality of memory cells and a plurality of conducting layers. The memory cells are three-dimensionally disposed on a semiconductor substrate. The conducting layers are disposed in a laminating direction. Each of the plurality of the conducting layers is connected to each of the plurality of the memory cells. Each conducting layer has a structure where a first conductive film and a second conductive film are laminated in the laminating direction. The conducting layers adjacent to one another in the laminating direction have a laminating order of the first conductive film and the second conductive film different from one another.Type: GrantFiled: August 4, 2016Date of Patent: March 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Fujiki, Takeshi Kamigaichi, Hideaki Aochi
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Publication number: 20180040742Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.Type: ApplicationFiled: August 4, 2017Publication date: February 8, 2018Applicant: Toshiba Memory CorporationInventors: Koji Matsuo, Gaku Sudo, Jun Nogami, Tatsuro Shinozaki, Takashi Ishida, Jun Fujiki, Kenzo Manabe
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Patent number: 9876029Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory strings arranged in a first direction intersecting a surface of a semiconductor substrate, each of the memory strings including a plurality of memory transistors connected in series in a second direction along the surface of the semiconductor substrate; a source side select transistor connected to one end of the memory string; a drain side select transistor connected to the other end of the memory string; a plurality of source lines respectively connected, via the source side select transistor, to each of the plurality of memory strings arranged along the first direction; a bit line commonly connected, via the drain side select transistor, to the plurality of memory strings arranged along the first direction; a word line connected to a gate electrode of the memory transistor; and a layer selector disposed between the source line and the source side select transistor and commonly connected to the plurality of memory strinType: GrantFiled: September 15, 2016Date of Patent: January 23, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Fujiki, Takeshi Kamigaichi, Hideaki Aochi
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Publication number: 20170278862Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory strings arranged in a first direction intersecting a surface of a semiconductor substrate, each of the memory strings including a plurality of memory transistors connected in series in a second direction along the surface of the semiconductor substrate; a source side select transistor connected to one end of the memory string; a drain side select transistor connected to the other end of the memory string; a plurality of source lines respectively connected, via the source side select transistor, to each of the plurality of memory strings arranged along the first direction; a bit line commonly connected, via the drain side select transistor, to the plurality of memory strings arranged along the first direction; a word line connected to a gate electrode of the memory transistor; and a layer selector disposed between the source line and the source side select transistor and commonly connected to the plurality of memory strinType: ApplicationFiled: September 15, 2016Publication date: September 28, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Jun FUJIKI, Takeshi KAMIGAICHI, Hideaki AOCHI
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Publication number: 20170263636Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.Type: ApplicationFiled: September 15, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takashi ISHIDA, Jun FUJIKI, Shinya ARAI, Fumitaka ARAI, Hideaki AOCHI, Kotaro FUJII
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Publication number: 20170263631Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type; a stacked body; a plurality of columnar portions; a plurality of first insulating portions having a wall configuration; and a plurality of second insulating portions having a columnar configuration. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body and a charge storage film. The first insulating portions extend in the stacking direction and in a first direction crossing the stacking direction. The second insulating portions extend in the stacking direction. A wide of the second insulating portions along a second direction crossing the first direction in a plane is wider than a wide of the first insulating portions along the second direction. The second insulating portions are disposed in a staggered lattice configuration.Type: ApplicationFiled: September 7, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Jun FUJIKI, Shinya Arai
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Patent number: 9761606Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.Type: GrantFiled: September 15, 2016Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Ishida, Jun Fujiki, Shinya Arai, Fumitaka Arai, Hideaki Aochi, Kotaro Fujii
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Publication number: 20170200734Abstract: One embodiment includes a plurality of memory cells and a plurality of conducting layers. The memory cells are three-dimensionally disposed on a semiconductor substrate. The conducting layers are disposed in a laminating direction. Each of the plurality of the conducting layers is connected to each of the plurality of the memory cells. Each conducting layer has a structure where a first conductive film and a second conductive film are laminated in the laminating direction. The conducting layers adjacent to one another in the laminating direction have a laminating order of the first conductive film and the second conductive film different from one another.Type: ApplicationFiled: August 4, 2016Publication date: July 13, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Jun Fujiki, Takeshi Kamigaichi, Hideaki Aochi
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Patent number: 9691786Abstract: A semiconductor memory device according to an embodiment includes: a first semiconductor layer; and a memory cell array on the first semiconductor layer, the memory cell array including a source line, a second semiconductor layer, and a conductive layer, those are sequentially disposed in a first direction and the memory cell array further including a third semiconductor layer which is columnar and extends in the first direction and a charge accumulation film disposed between the conductive layer and the third semiconductor layer, wherein the second semiconductor layer includes a first impurity region of a first conductivity type disposed at a position of the third semiconductor layer as viewed from the first direction and a second impurity region adjacent to the first impurity region which has a second conductivity type different from the first conductivity type.Type: GrantFiled: August 31, 2016Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masaki Tsuji, Hideaki Aochi, Jun Fujiki
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Patent number: 9620653Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: December 16, 2015Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Publication number: 20160268304Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.Type: ApplicationFiled: March 11, 2016Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Keiji IKEDA, Masumi SAITOH, Hideaki AOCHI, Takeshi KAMIGAICHI, Jun FUJIKI
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Publication number: 20160104802Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: December 16, 2015Publication date: April 14, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Patent number: 9252290Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: March 16, 2015Date of Patent: February 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Patent number: 9252291Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.Type: GrantFiled: March 23, 2011Date of Patent: February 2, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Jun Fujiki, Naoki Yasuda, Daisuke Matsushita
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Patent number: 9246014Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: March 16, 2015Date of Patent: January 26, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Patent number: 9211472Abstract: A game device includes a light control unit configured to change, in a game field in which an object is located, a position of a light source or a direction of radiation by light emitted from the light source based on a control command of a player, a shadow rendering unit configured to render a shadow of the object projected by light emitted from the light source onto a plane of projection defined in the game field; and a character control unit configured to move a character along the shadow of the object.Type: GrantFiled: February 7, 2011Date of Patent: December 15, 2015Assignees: Sony Corporation, Sony Computer Entertainment Inc.Inventors: Ken Suzuta, Tatsuya Suzuki, Jun Fujiki, Takanori Kikuchi