Patents by Inventor Jun Fujiki
Jun Fujiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220199641Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically oveType: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
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Publication number: 20220180937Abstract: An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.Type: ApplicationFiled: December 4, 2020Publication date: June 9, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Publication number: 20220180938Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of aType: ApplicationFiled: December 4, 2020Publication date: June 9, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Publication number: 20220181346Abstract: Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.Type: ApplicationFiled: December 21, 2021Publication date: June 9, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Publication number: 20220180939Abstract: Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.Type: ApplicationFiled: December 4, 2020Publication date: June 9, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Patent number: 11322516Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.Type: GrantFiled: August 31, 2020Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
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Publication number: 20220068955Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
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Patent number: 11227869Abstract: Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.Type: GrantFiled: December 4, 2020Date of Patent: January 18, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Publication number: 20210280603Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Applicant: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Patent number: 11049878Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: July 14, 2020Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Publication number: 20210126003Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: ApplicationFiled: January 7, 2021Publication date: April 29, 2021Applicant: Toshiba Memory CorporationInventors: Kotaro FUJII, Jun FUJIKI, Shinya ARAI
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Patent number: 10923490Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: GrantFiled: January 9, 2020Date of Patent: February 16, 2021Assignee: Toshiba Memory CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20200343264Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Patent number: 10756104Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: September 12, 2018Date of Patent: August 25, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Publication number: 20200144278Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Applicant: Toshiba Memory CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Patent number: 10608009Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.Type: GrantFiled: March 11, 2016Date of Patent: March 31, 2020Assignee: Toshiba Memory CorporationInventors: Keiji Ikeda, Masumi Saitoh, Hideaki Aochi, Takeshi Kamigaichi, Jun Fujiki
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Patent number: 10566339Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: GrantFiled: August 31, 2017Date of Patent: February 18, 2020Assignee: Toshiba Memory CoporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20190338125Abstract: An object of the present invention is to provide a resin composition having excellent heat resistance and excellent thermal adhesiveness, so as to provide an electric insulating sheet having excellent heat resistance. In order to achieve the aforementioned object, the present invention provides a resin composition which contains a polyether sulfone resin and a resin having a specific melt viscosity, and contains at least a phenoxy resin other than the polyether sulfone resin.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Applicant: Nitto Shinko CorporationInventors: Yasuyuki Kihara, Takahiro Sakaguchi, Jun Fujiki
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Publication number: 20190198524Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: ApplicationFiled: September 12, 2018Publication date: June 27, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Jun FUJIKI, Shinya ARAI, Kotaro FUJII
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Patent number: 10283647Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.Type: GrantFiled: August 4, 2017Date of Patent: May 7, 2019Assignee: Toshiba Memory CorporationInventors: Koji Matsuo, Gaku Sudo, Jun Nogami, Tatsuro Shinozaki, Takashi Ishida, Jun Fujiki, Kenzo Manabe