Patents by Inventor Jun-hee Cho

Jun-hee Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7638398
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7585727
    Abstract: A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion of the recess is isotropically etching to form a bulb-shaped recess.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20090163000
    Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.
    Type: Application
    Filed: June 30, 2008
    Publication date: June 25, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jun-Hee CHO, Sang-Hoon PARK
  • Publication number: 20080305608
    Abstract: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region.
    Type: Application
    Filed: December 26, 2007
    Publication date: December 11, 2008
    Inventor: Jun-Hee Cho
  • Patent number: 7449392
    Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 11, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yil Wook Kim, Jun Hee Cho, Sung Eon Park, Jin Hong Ahn, Sang Don Lee
  • Publication number: 20080230832
    Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 25, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee CHO
  • Publication number: 20080087980
    Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.
    Type: Application
    Filed: December 4, 2007
    Publication date: April 17, 2008
    Inventor: Jun-Hee Cho
  • Patent number: 7354828
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 8, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7348255
    Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: March 25, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20080006881
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Application
    Filed: August 13, 2007
    Publication date: January 10, 2008
    Inventor: Jun-Hee Cho
  • Patent number: 7301207
    Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: November 27, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yil Wook Kim, Jun Hee Cho, Sung Eon Park, Jin Hong Ahn, Sang Don Lee
  • Publication number: 20070228461
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Application
    Filed: December 28, 2006
    Publication date: October 4, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20070232042
    Abstract: A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion of the recess is isotropically etching to form a bulb-shaped recess.
    Type: Application
    Filed: December 28, 2006
    Publication date: October 4, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20070148980
    Abstract: A method for fabricating a semiconductor device with a bulb-shaped recess gate pattern is provided. The method includes forming a plurality of oxide layers over a substrate; forming a silicon layer to cover the oxide layers; forming a mask over the silicon layer; etching the silicon layer using the mask as an etch mask to form a plurality of first recesses to expose the oxide layers; etching the oxide layers to form a plurality of second recesses; and forming a plurality of gate patterns at least partially buried into the first recesses and the second recesses.
    Type: Application
    Filed: April 28, 2006
    Publication date: June 28, 2007
    Inventor: Jun-Hee Cho
  • Publication number: 20060292819
    Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.
    Type: Application
    Filed: December 28, 2005
    Publication date: December 28, 2006
    Inventor: Jun-Hee Cho
  • Publication number: 20060220145
    Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
    Type: Application
    Filed: December 29, 2005
    Publication date: October 5, 2006
    Inventor: Jun-Hee Cho
  • Publication number: 20050280113
    Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
    Type: Application
    Filed: December 9, 2004
    Publication date: December 22, 2005
    Inventors: Yil Kim, Jun Hee Cho, Sung Eon Park, Jin Hong Ahn, Sang Don Lee
  • Patent number: 6920305
    Abstract: A device for and a method of cleaning a photoreceptor medium of an electrophotographic image forming apparatus include a magnet which is installed in a lengthwise direction of the photoreceptor medium and is separated from an outer surface of the photoreceptor medium, and a magnetic fluid which fills a space between the magnet and the outer surface of the photoreceptor medium and closely contacts the outer surface of the photoreceptor medium. Accordingly, abrasion of the photoreceptor medium can be prevented, and since the developer does not stick to the magnetic fluid, a decrease in a cleaning efficiency can be prevented.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: July 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-young Byun, Jun-hee Cho
  • Patent number: 6887788
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method comprises the steps of: preparing a silicon substrate having a predetermined lower structure including a gate and a bonding area; forming an interlayer dielectric film on the top side of the substrate; forming a photosensitive film pattern, which exposes an area for providing contact, on the interlayer dielectric film; forming a contact hole exposing a bonding area of the substrate by etching the exposed part of the interlayer dielectric film; removing the photosensitive film pattern; performing a dry cleaning on the exposed bonding area of the substrate so that CF based polymer formed in the etching step is removed; and performing a nitrogen-hydrogen plasma processing on the surface of the exposed bonding area of the substrate so that oxygen polymer and remaining CF-based polymer are removed. Therefore, since hydrogen plasma processing is performed after contact etching, ohmic contact characteristics can be secured.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: May 3, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun Hee Cho, Il Wook Kim, Seok Kiu Lee, Tae Hang Ahn, Sung Eon Park
  • Patent number: 6862419
    Abstract: A liquid image developing system, including a cartridge in which a developer is stored; a supply line; a development container to which the developer is supplied from the cartridge through the supply line; a photosensitive body in the development container; a development roller partially soaked in the developer in the development container and rotating opposite to the photosensitive body; a depositing member to create a potential difference required to attach the developer to a circumference of the development roller, opposite to the development roller; a metering blade to scratch the developer attached to the circumference of the development roller to a predetermined thickness; and an agitator to agitate the developer contained in the development container. Accordingly, a high-concentration developer can be directly used in the development operation without a dilution operation, and thus the structure to supply the developer can be considerably simplified.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: March 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-hee Cho, Yong-su Kim