Patents by Inventor Jun Iijima

Jun Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350291
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Application
    Filed: June 30, 2020
    Publication date: November 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
  • Publication number: 20200343263
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Publication number: 20200295037
    Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Iijima, Masayoshi Tagami, Shinya Arai, Takahiro Tomimatsu
  • Patent number: 10748928
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10744787
    Abstract: A liquid droplet discharging apparatus includes a plurality of nozzles to discharge a liquid droplet onto a medium and a liquid droplet discharging controller to receive image data. The liquid droplet discharging controller controls each of the nozzles to discharge the liquid droplet in an amount defined by the image data onto a target discharging position on the medium, which corresponds to a pixel position defined by the image data. The liquid droplet discharging controller controls at least one of the nozzles to discharge the liquid droplet for a controlled number of times smaller than a number of times N representing an integer not smaller than 2 in an amount greater than the amount defined by the image data onto the target discharging position on the medium. A frequency recorder records the controlled number of times of discharging for each of the at least one of the nozzles.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 18, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventors: Yasunari Harada, Jun Watanabe, Tetsuyoshi Nakata, Hideaki Iijima, Toshiaki Hosokawa, Shunsuke Shitaoka
  • Patent number: 10741527
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Patent number: 10741358
    Abstract: An electron microscope comprises: an electron microscope main body including a phase plate that imparts a phase change to an electron wave, a moving mechanism that moves the phase plate, and a detector that acquires an image formed by an electron beam transmitted through a sample; and a control unit that controls the electron microscope main body. The control unit performs a phase plate image acquisition process of acquiring a phase plate image which is an image of the phase plate; an unevenness determination process of determining whether or not the phase plate has unevenness based on the phase plate image; and a moving mechanism control process of moving the phase plate by controlling the moving mechanism when the control unit has determined that the unevenness is present.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 11, 2020
    Assignee: JEOL Ltd.
    Inventors: Yuko Shimizu, Hirofumi Iijima, Naoki Hosogi, Jun Yamashita
  • Publication number: 20200176434
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Yumi NAKAJIMA
  • Publication number: 20200119404
    Abstract: Provided is a semisolid electrolyte solution to improve a battery capacity of a secondary battery. The semisolid electrolyte solution includes: a solvated electrolyte salt; and an ether-based solvent that constitutes the solvated electrolyte salt and a solvated ion liquid, in which a mixing ratio of the ether-based solvent to the solvated electrolyte salt is larger than 0 and equal to or less than 0.5 in terms of a molar ratio. Desirably, the mixing ratio of the ether-based solvent to the solvated electrolyte salt is 0.2 to 0.5 in terms of the molar ratio. When a low viscosity solvent is provided, a mixing ratio of the low viscosity solvent to the solvated electrolyte salt is 2 to 6 in terms of the molar ratio.
    Type: Application
    Filed: March 16, 2018
    Publication date: April 16, 2020
    Inventors: Suguru UEDA, Atsushi UNEMOTO, Akihide TANAKA, Atsushi IIJIMA, Jun KAWAJI
  • Publication number: 20200111810
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10600771
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Iijima, Yumi Nakajima
  • Publication number: 20200075325
    Abstract: Examples of a film forming method include placing a substrate on a susceptor arranged in a chamber, and introducing a hydrogen-containing gas and a nitrogen gas into the chamber, and applying radio frequency power to an electrode above the susceptor to generate plasma, and form a nitride film on the substrate, wherein a flow rate of the hydrogen-containing gas is equal to 1% or less of a flow rate of the nitrogen gas.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 5, 2020
    Applicant: ASM IP Holding B.V.
    Inventors: Toshiaki IIJIMA, Jun KAWAHARA
  • Patent number: 10553612
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Publication number: 20200013582
    Abstract: An electron microscope comprises: an electron microscope main body including a phase plate that imparts a phase change to an electron wave, a moving mechanism that moves the phase plate, and a detector that acquires an image formed by an electron beam transmitted through a sample; and a control unit that controls the electron microscope main body. The control unit performs a phase plate image acquisition process of acquiring a phase plate image which is an image of the phase plate; an unevenness determination process of determining whether or not the phase plate has unevenness based on the phase plate image; and a moving mechanism control process of moving the phase plate by controlling the moving mechanism when the control unit has determined that the unevenness is present.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 9, 2020
    Inventors: Yuko Shimizu, Hirofumi Iijima, Naoki Hosogi, Jun Yamashita
  • Publication number: 20200014067
    Abstract: Aiming at improvement in the life and rate characteristic of the secondary battery, the semisolid electrolytic solution, the semisolid electrolyte layer, the electrode, and the secondary battery are provided. The semisolid electrolytic solution contains a solvation electrolyte salt, an ethereal solvent for forming a solvation ion liquid together with the solvation electrolyte salt, and a low-viscosity solvent. The mixture molar ratio of the ethereal solvent to the solvation electrolyte salt is in the range from ?0.5 to ?1.5. The mixture molar ratio of the low-viscosity solvent to the solvation electrolyte salt is in the range from ?4 to ?16.
    Type: Application
    Filed: February 19, 2018
    Publication date: January 9, 2020
    Inventors: Suguru UEDA, Jun KAWAJI, Atsushi IIJIMA, Atsushi UNEMOTO, Akihide TANAKA
  • Patent number: 10479105
    Abstract: A droplet discharge apparatus to discharge droplets while moved by a user includes a head to discharge a droplet onto a recording medium, a sensor to detect a movement amount of the droplet discharge apparatus in a predetermined period, and a memory to store determination information indicating whether droplet discharging has been instructed for each pixel of the image data. The droplet discharge apparatus further includes a processor configured to accumulate the movement amount to calculate a total movement amount of the droplet discharge apparatus; instruct droplet discharging from the head based on the total movement amount and the image data; instruct droplet discharging only for an unprinted pixel for which the determination information indicates that droplet discharging has not been instructed; and rewrite the determination information of the unprinted pixel to indicate that droplet discharging has been instructed, based on a predetermined condition.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 19, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Toshiaki Hosokawa, Jun Watanabe, Tetsuyoshi Nakata, Yasunari Harada, Hideaki Iijima, Shunsuke Shitaoka
  • Publication number: 20190326322
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
  • Publication number: 20190312012
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 10, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
  • Publication number: 20190296035
    Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Masayoshi Tagami, Takamasa Usui, Takahito Nishimura
  • Publication number: 20190287955
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Yumi NAKAJIMA