Patents by Inventor Jun Kojima

Jun Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050230686
    Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate having a principal surface and a backside surface; a drift layer disposed on the principal surface; a base region disposed on the drift layer; a source region disposed on the base region; a surface channel layer disposed on both of the drift layer and the base region for connecting between the source region and the drift layer; a gate insulation film disposed on the surface channel layer and including a high dielectric constant film; a gate electrode disposed on the gate insulation film; a source electrode disposed on the source region; and a backside electrode disposed on the backside surface.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 20, 2005
    Inventors: Jun Kojima, Takeshi Endo, Eiichi Okuno, Yoshihito Mitsuoka, Yoshiyuki Hisada, Hideo Matsuki
  • Patent number: 6657827
    Abstract: A head includes a head chip, having first and second external connection electrodes, for reading a signal from a storage medium and writing a signal on the storage medium, a substrate having the head chip mounted thereon, a hot-side conductor path and a ground-side conductor path each formed on the surface of the substrate and electrically connected to the corresponding external connection electrodes of the head chip, and a chip varistor, mounted on the substrate, having first, second, and third terminal electrodes, the third terminal electrode being connected to the ground. In the head, the hot-side conductor path is divided, and the corresponding conductor parts of ends of the divided hot-side conductor paths are electrically connected to the first and the second terminal electrodes, and the ground-side conductor path is electrically connected to the third terminal electrode of the chip varistor.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: December 2, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsumasa Fukuda, Yukio Sakamoto, Jun Kojima
  • Patent number: 6573534
    Abstract: A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said s
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: June 3, 2003
    Assignee: Denso Corporation
    Inventors: Rajesh Kumar, Tsuyoshi Yamamoto, Shoichi Onda, Mitsuhiro Kataoka, Kunihiko Hara, Eiichi Okuno, Jun Kojima
  • Patent number: 6551865
    Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: April 22, 2003
    Assignee: Denso Corporation
    Inventors: Rajesh Kumar, Hiroki Nakamura, Jun Kojima
  • Publication number: 20020139992
    Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Inventors: Rajesh Kumar, Hiroki Nakamura, Jun Kojima
  • Patent number: 6245820
    Abstract: A medicine for the treatment of Meniere's disease containing, as an active ingredient, erythritol which is capable of significantly reducing the endolymphatic pressure by oral administration of a therapeutically effective amount of erythritol as an active substance.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: June 12, 2001
    Assignee: Nikken Chemicals, Co., LTD
    Inventors: Jun Kojima, Shingo Yanagida, Takeshi Otani
  • Patent number: 6221700
    Abstract: A surface portion of a p type base region is made amorphous as an amorphous layer by implanting nitrogen ions which serve as impurities and ions which do not serve as impurities. After that, the amorphous layer is crystallized to have a specific crystal structure through solid-phase growth while disposing the impurities at lattice positions of the crystal structure. As a result, a surface channel layer is formed with a high activation rate of the impurities.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: April 24, 2001
    Assignee: Denso Corporation
    Inventors: Eiichi Okuno, Jun Kojima
  • Patent number: 5886999
    Abstract: A demultiplexer separates the data obtained by the demodulation into the data for each information medium, and a synchronous word detection state monitor detects the synchronous word contained in a received signal of a predetermined information medium and compares the state in which said synchronous word is detected with the preset standard, and outputs an output stop signal when the synchronous word detection state is worse then the preset standard.An error-correction decoder subjects the data obtained by the demodulation to an error-correction decoding processing, and an error-correction encoder subjects the decoded data to an error-correction encoding processing. A line quality estimating portion estimates the quality of the line by comparing the data obtained by the error-correction encoding processing with the demodulated data before decoding and an output controller stops outputting the received signal to the external terminal when the line quality is worse than the reference quality.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: March 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Jun Kojima, Mitsuru Seta, Tomoyuki Ueno